PIC18LF2410T-I/SO Microchip Technology, PIC18LF2410T-I/SO Datasheet - Page 34

IC MCU FLASH 8KX16 28SOIC

PIC18LF2410T-I/SO

Manufacturer Part Number
PIC18LF2410T-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2410T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
PIC18F2X1X/4X1X
3.1.3
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Three bits indicate the current clock source and its
status. They are:
• OSTS (OSCCON<3>)
• IOFS (OSCCON<2>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is
providing a stable 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC3:FOSC0 Configura-
tion bits, then both the OSTS and IOFS bits may be set
when in PRI_RUN or PRI_IDLE modes. This indicates
that the primary clock (INTOSC output) is generating a
stable 8 MHz output. Entering another power-managed
RC mode at the same frequency would clear the OSTS
bit.
3.1.4
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39636D-page 36
Note 1: Caution should be used when modifying a
2: Executing a SLEEP instruction does not
CLOCK TRANSITIONS AND
STATUS INDICATORS
MULTIPLE SLEEP COMMANDS
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
DD
/F
OSC
specifications are violated.
DD
is less than 3V, it is
DD
.
3.2
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled (see Section 22.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 2.7.1 “Oscillator
Control Register”).
3.2.2
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
Note:
Run Modes
PRI_RUN MODE
SEC_RUN MODE
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
© 2009 Microchip Technology Inc.

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