ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet
ATA6613P-PLQW
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ATA6613P-PLQW Summary of contents
Page 1
... In section 2 you will find the pin configuration for the complete SiP. In sections the LIN SBC is described, and in sections the Atmel AVR is described in detail. Figure 1-1. Application Diagram ...
Page 2
... Receive data output (1) 18 INH High side switch output for controlling an external voltage regulator (1) 19 TXD Transmit data input / active low output after a local wake up request Note: 1. This identifies the pins of the LIN SBC Atmel ATA6624 Atmel ATA6612/ATA6613 2 7mm PB5 1 MCUAVDD 2 ADC6 ...
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... Port B 1 I/O line (OC1A/PCINT1) 46 PB2 Port B 2 I/O line (OC1B/SS/PCINT2) 47 PB3 Port B 3 I/O line (MOSI/OC2A/PCINT3) 48 PB4 Port B 4 I/O line (MISO/PCINT4) Backside Heat slug is connected to GND Note: 1. This identifies the pins of the LIN SBC Atmel ATA6624 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 3 ...
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... Thermal resistance junctiion to ambient Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Note means the temperature of the heat slug (backside mandatory that this backside temperature is 125°C in the case application. Atmel ATA6612/ATA6613 4 Symbol Min. Typ. ±2 ±750 T –55 ...
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... The LIN-SBC is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data com- munication up to 20kBaud. Sleep Mode and Silent Mode guarantee very low current consumption. 9111H–AUTO–01/ 27V S = 5.0V ± Switched Off CC Atmel ATA6612/ATA6613 5 ...
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... Normal and Fail-safe Mode INH PVCC RXD WAKE Edge KL_15 Detection PVCC TXD Time-out TXD Timer Debounce EN Time GND Atmel ATA6612/ATA6613 6 Receiver - + Wake-up Bus Timer Slew Rate Control Control Unit Mode Select Internal Testing Watchdog Unit PVCC MODE TM NTRIG Normal Mode ...
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... GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 = 5V to 27V. An undervoltage detection is implemented to dis- S falls below VS < ...
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... Connect the MODE pin directly or via an external resistor to GND for normal watchdog opera- tion. To debug the software of the connected microcontroller, connect the MODE pin to VCC and the watchdog is switched off. 3.3.13 TM Input Pin The TM pin is used for final production measurements at Atmel. In normal application, it has to be always connected to GND. Atmel ATA6612/ATA6613 8 > 6ms, DOM = 0V) ...
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... IC into Sleep or Silent Mode. Connect the Batt . To protect this pin against voltage transients, a serial resistor and a KL_15 and, therefore, the sensitivity against transients on the ignition Kl.15. KL_15 to generate a watchdog trigger. trigmin Atmel ATA6612/ATA6613 undervoltage Kl_15 9 ...
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... Modes of Operation Normal Mode VCC: 5V/50mA With undervoltage monitoring Communication: ON Watchdog: ON Table 3-1. Mode of Operation Fail-safe Normal Silent Sleep Atmel ATA6612/ATA6613 10 Unpowered Mode Batt b a Fail-safe Mode VCC: 5V/50mA With undervoltage monitoring Communication: OFF Watchdog silent command TXD = 1 Local wake-up event ...
Page 11
... Switch to Silent Mode Normal Mode EN Mode select window TXD t = 3.2µs d NRES VCC Delay time silent mode t _sleep = maximum 20µs d LIN LIN switches directly to recessive mode Atmel ATA6612/ATA6613 Figure 3-3 on page 11). The transmission is a combination of the Batt . VCC Silent Mode pin ...
Page 12
... LOW than the TXD. Therefore, the best and easiest way are two falling edges at TXD and EN at the same time.The transmission path is disabled in Sleep Mode. The supply current I Atmel ATA6612/ATA6613 12 ) and the following rising edge at the LIN pin (see ...
Page 13
... Delay time sleep mode t = maximum 20µs d_sleep LIN LIN switches directly to recessive mode Figure 3-7 on page (V < 4V) during Silent or Sleep Mode switches the IC into Fail-safe Mode. A low Batt S Atmel ATA6612/ATA6613 Figure 3-6 on page 14). Sleep Mode 17). The NRES output switches to low for pin ...
Page 14
... The NRES is low for the reset time delay t possible. Figure 3-6. LIN bus RXD TXD VCC voltage regulator NRES Watchdog Atmel ATA6612/ATA6613 14 Figure 3-7 on page , the IC mode changes from Unpowered Mode to Fail-safe Mode. th LIN Wake-up from Sleep Mode Bus wake-up filtering time t bus Low or floating Off state ...
Page 15
... LIN result in a remote wake-up request. The device BUS ) results in a local wake-up request. The device switches to Fail-safe Mode. The local and Figure 3-4 on page Atmel ATA6612/ATA6613 at the LIN pin activates the internal LIN LINL maintained for a certain BUSdom 12) and the Normal Mode ...
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... Figure 3-8 on page 17 . Due to BUS_LIM , and the LIN output is switched LINoff , switches the output on again. RXD hys or GND. This is Batt . Because of VCCn , the VCC VCCoff , switches the output hys , which is VCC the safe operating area of the Atmel 9111H–AUTO–01/11 ® ...
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... VCC Reset NRES 5V Power Dissipation: Safe Operating Area versus VCC Output Current and Sup- ply Voltage V at Different Ambient Temperatures Due Atmel ATA6612/ATA6613 T res_f = 25 K/W thja T = 105°C amb T = 110°C amb T = 115°C amb Pin of the system basis chip is disconnected. S Pin of the system basis chip is disconnected ...
Page 18
... If the triggering signal fails in this open window t the NRES output will be drawn to ground. A triggering signal during the closed window t immediately switches NRES to low. Atmel ATA6612/ATA6613 18 > 200ns triggering signal is not received, a reset signal will be generated at output (34k to 120k ) ...
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... Period Time Window t /µs t /ms t /ms osc d 1 13.3 105 14.0 19.61 154.8 20.64 33.54 264.80 35.32 42.84 338.22 45.11 Atmel ATA6612/ATA6613 Watchdog Reset 21ms 2 and t can also vary by 20 calculated as follows. wd and the minimum 24.8ms 26ms 2 Trigger Period Open Window ...
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... Pin WAKE (33 k serial resistor) to GND ESD HBM following STM5.1 with 1.5k 100pF - Pin VS, LIN, WAKE to GND HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Machine Model ESD AEC-Q100-RevF(003) Junction temperature Storage temperature Atmel ATA6612/ATA6613 20 Symbol Min. Typ. V –0 – ...
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... < 14V VS S < 14V VS S load current 50mA CC < 14V RXD LIN = 0.4V RXD = 1mA RXD RXD TXD TXD = 0V TXD TXD = VCC TXD TXD Atmel ATA6612/ATA6613 Symbol Min. Typ. Max VSsleep VSsleep VSsi VSsi I 0.3 0.8 VSrec I 50 ...
Page 22
... Driver dominant voltage R V 8.4 Driver dominant voltage R V 8.5 Driver dominant voltage R *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Atmel ATA6612/ATA6613 22 < 150°C, unless otherwise specified. All values refer to GND pins j Pin = V LIN S TXD = 0V WAKE = 0 ...
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... GND LIN I SUP_Device < 18V BUS = BUS_CNT LIN + V _ )/2 th_dom th rec = 5V LIN LIN – V LIN hys th_rec th_dom LIN LIN Atmel ATA6612/ATA6613 Symbol Min. Typ. Max LIN V 0.4 1.0 SerDiode I 40 120 200 BUS_LIM –1 –0. BUS_PAS_rec –10 +0.5 +10 BUS_NO_gnd 0.1 BUS_NO_bat ...
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... Symmetry of receiver V 11.2 propagation delay rising t rx_sym edge minus falling edge *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Atmel ATA6612/ATA6613 24 < 150°C, unless otherwise specified. All values refer to GND pins j Pin = 0V LIN LIN = ...
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... OSC = 91k OSC = 120k OSC OSC NRES KL_15 KL_15 < 27V S KL_15 = 27V KL_15 KL_15 = 47k , C = 100nF KL_15 V WAKE WAKE < 27V S WAKE = 0V WAKE Atmel ATA6612/ATA6613 Symbol Min. Typ. Max. V 0.2 NRESL 0.14 V 0.2 NRESLL reset t 1.5 10 res_f V 1.13 1.23 1.33 WD_OSC ...
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... Referred to VCC 18.12 undervoltage threshold V Ramp-up time V > 5. 18. load *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Atmel ATA6612/ATA6613 26 < 150°C, unless otherwise specified. All values refer to GND pins j Pin = 27V S WAKE = 27V WAKE = 0V WAKE WAKE < 18V S VCC < ...
Page 27
... TH Rec(max Dom(max) (Transceiver supply of transmitting node) TH Rec(min) TH Dom(min) RXD (Output of receiving node1) t rx_pdf(1) RXD (Output of receiving node2) 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 t t Bit Bit t Bus_dom(max) LIN Bus Signal t Bus_dom(min) t rx_pdr(2) t Bit t Bus_rec(min) Thresholds of receiving node1 Thresholds of receiving node2 ...
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... Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier • Non-volatile Program and Data Memories – 8/16 Kbytes of In-System Self-programmable Flash (Atmel ATA6612/ATA6613) – Optional Boot Code Section with Independent Lock Bits – 512Bytes EEPROM – 1Kbyte Internal SRAM – Programming Lock for Software Security • ...
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... Overview The Atmel Atmel AVR cycle, the Atmel ATA6612/ATA6613 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 6.2.1 Block Diagram Figure 6-1. Block Diagram 9111H–AUTO–01/11 ® ATA6612/ATA6613 uses a low-power CMOS 8-bit microcontroller based on the ® ...
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... On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip Boot program running on the Atmel AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation ...
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... Comparison Between Atmel ATA6612/ATA6613 The Atmel interrupt vector sizes. for the two devices. Table 6-1. Atmel ATA6612 and ATA6613 support a real Read-While-Write Self-Programming mecha- nism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. 6.2.4 Pin Descriptions 6 ...
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... ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. Atmel ATA6612/ATA6613 32 101. 104. is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. I should be exter- , even if the ADC is not used ...
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... This section discusses the Atmel AVR CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.4.2 Architectural Overview Figure 6-2. Block Diagram of the Atmel AVR Architecture Flash program memory Instruction register ...
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... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel ATA6612/ATA6613 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 35
... Bit 4 – S: Sign Bit The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple- ment Overflow Flag V. See the “Instruction Set Description” for detailed information. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 ® ALU operates in direct connection with all the 32 general pur- 7 ...
Page 36
... Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 6-3 Figure 6-3. General Purpose Working Registers Atmel ATA6612/ATA6613 36 shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers ...
Page 37
... Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 Figure 6-3 on page 36, each register is also assigned a data memory address, The X-, Y-, and Z-registers ...
Page 38
... Figure 6-5. Figure 6-6 on page 39 cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Atmel ATA6612/ATA6613 38 ® architecture is so small that only SPL is needed. In this case, the SPH 15 ...
Page 39
... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse (see Self-Programming, Atmel ATA6612 and ATA6613” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Atmel ATA6612/ATA6613 40 in r16, SREG ; store SREG value ...
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... ATA6612 and ATA6613. See SELFPRGEN description in section Control and Status Register – SPMCSR” on page 289 The Flash memory has an endurance of at least 75,000 write/erase cycles. The Atmel ATA6612/ATA6613 Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Self-Programming, Atmel ATA6612 and ATA6613” ...
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... Figure 6-8. Atmel ATA6612/ATA6613 42 ® Program Memory Map, Atmel ATA6612/ATA6613 Program Memory Application Flash Section Boot Flash Section 0x0000 0x0FFF/0x1FFF 9111H–AUTO–01/11 ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512/1024/1024 bytes of internal data SRAM in the Atmel ATA6612/ATA6613 are all acces- sible through all these addressing modes. The Register File is described in Register File” ...
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... Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. Atmel ATA6612/ATA6613 44 T1 clk ...
Page 45
... Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the Atmel ATA6612/ATA6613 and will always read as zero • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE ...
Page 46
... Loader Support – Read-While-Write Self-Programming, Atmel Table 6-2. While EEPE is Operation Erase and Write in one operation (Atomic Operation) Erase Only Write Only Reserved for future use for details about Boot programming. 9111H–AUTO–01/11 ...
Page 47
... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ...
Page 48
... Assembly Code Example C Code Example The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execu- tion of these functions. Atmel ATA6612/ATA6613 48 EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ...
Page 49
... Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; } the EEPROM data can be corrupted because the supply voltage is CC, ® RESET active (low) during periods of insufficient power supply voltage. This Atmel ATA6612/ATA6613 reset Protection CC 49 ...
Page 50
... The I/O space definition of the Atmel page All Atmel ATA6612/ATA6613 I/Os and peripherals are placed in the I/O space. All I/O loca- tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 51
... ASY System Clock Prescaler Source clock Clock Multiplexer Timer/Counter External Clock Oscillator is halted, TWI address recognition in all sleep modes. I/O Atmel ATA6612/ATA6613 ® and their distribution. All of the CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer ...
Page 52
... Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in quency of the Watchdog Oscillator is voltage dependent as shown in page Atmel ATA6612/ATA6613 52 ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
Page 53
... If this is not possible, an internal or external Brown-Out Detection circuit CC is assumed sufficient level and only the start-up time is included. CC 55. Table 6-6 on page C2 C1 54. Atmel ATA6612/ATA6613 = 3.0V) Number of Cycles CC 0ms 4.3ms 4K (4,096) 69ms 8K (8,192) ® in reset until it is supplied with minimum V ...
Page 54
... Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: Atmel ATA6612/ATA6613 54 Low Power Crystal Oscillator Operating Modes (1) Frequency Range (MHz) CKSEL3..1 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 1 ...
Page 55
... If 8 MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device Atmel ATA6612/ATA6613 Figure 6-12 on page 53. Note that the Full Swing Crystal 56. For ceramic resonators, the capacitor Table ...
Page 56
... Table 6-10. Power Conditions BOD enabled Fast rising power Slowly rising power BOD enabled Fast rising power Slowly rising power Note: Atmel ATA6612/ATA6613 56 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ...
Page 57
... Reserved 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4.1ms to ensure programming mode can be entered. The device is shipped with this option selected. 2. Atmel ATA6612/ATA6613 for more details. This clock may be selected as the Table 6-11. If selected, it will (1)(3) CKSEL3..0 ...
Page 58
... C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 6-13. Note: When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-14 on page Atmel ATA6612/ATA6613 58 Bit CAL7 ...
Page 59
... NC EXTERNAL CLOCK SIGNAL 6-16. Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save 6CK 6CK 6CK Reserved Atmel ATA6612/ATA6613 Additional Delay from Reset (1) 14CK 14CK + 4ms 14CK + 64ms Figure 6-14. To run the device on Table 6-15. (2) Recommended Range for Capacitors C1 ...
Page 60
... From the time the CLKPS values are written, it takes between and before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here the previous clock period, and T2 is the period corresponding to the new prescaler setting. Atmel ATA6612/ATA6613 60 for details. ...
Page 61
... The device is shipped with the CKDIV8 Fuse programmed. 9111H–AUTO–01/11 CLKPR to zero. Bit CLKPCE – – R Table 6-17 on page Atmel ATA6612/ATA6613 – CLKPS3 CLKPS2 CLKPS1 CLKPS0 R R/W R/W R/W 0 See Bit Description 62. 0 CLKPR R/W 61 ...
Page 62
... SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector ATA6612/ATA6613, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Atmel ATA6612/ATA6613 62 Clock Prescaler Select CLKPS2 CLKPS1 ...
Page 63
... The Sleep Mode Control Register contains control bits for power management. Read/Write Initial Value • Bits 7..4 Res: Reserved Bits These bits are unused bits in the Atmel zero. • Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 6-18 ...
Page 64
... If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2. Atmel ATA6612/ATA6613 64 for details. “Clock Sources” on page ...
Page 65
... Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains Oscillators (1) 1. Only recommended with external crystal or resonator selected as clock source Timer/Counter2 is running in asynchronous mode. 3. For INT1 and INT0, only level interrupt. “Power-down Supply Current” on page 330 Atmel ATA6612/ATA6613 Wake-up Sources ( (2) ( ...
Page 66
... Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 4 - Res: Reserved bit This bit is reserved in Atmel • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • ...
Page 67
... In general, sleep modes should be used as much as possible, “Analog Comparator” on page 262 for details on the start-up time. “Watchdog Timer” on page 74 Atmel ATA6612/ATA6613 “Analog-to-Digital Converter” on page 265 for details on how to “Brown-out Detection” on page 71 for details on how to configure the Watchdog for “ ...
Page 68
... During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the Atmel must be a JMP – Absolute Jump – instruction to the reset handling routine. For the Atmel ATA6612, the instruction placed at the Reset Vector must be an RJMP – Relative Jump – ...
Page 69
... ATA6612/ATA6613 has four sources of reset: ). POT ) and the Brown-out Detector is enabled. BOT DATA BUS MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit Reset Circuit Watchdog Timer Watchdog Oscillator Delay Counters Clock CK Generator CKSEL[3:0] SUT[1:0] Atmel ATA6612/ATA6613 is below the Brown-out TIMEOUT 69 ...
Page 70
... VCC Rise Rate to ensure Power-on Reset CCRR V RESET Pin Threshold Voltage RST Note: 1. Before rising, the supply has to be between Atmel ATA6612/ATA6613 70 Table 6-20. The POR is activated whenever V rise. The RESET signal is activated again, without any CC decreases below the detection level. ...
Page 71
... V This guarantees that a Brown-Out Reset will occur before V rect operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 and BODLEVEL = 101 for Atmel ATA6612V/ATA6613V, and BODLEVEL = 101 and BODLEVEL = 101 for Atmel ATA6612/ATA6613 70) will generate a reset, even if the clock is not – ...
Page 72
... On the falling edge of this pulse, the delay timer starts counting the Time-out period t Refer to Figure 6-20. Watchdog System Reset During Operation RESET TIME-OUT RESET TIME-OUT INTERNAL RESET Atmel ATA6612/ATA6613 72 Brown-out Characteristics Parameter Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset decreases to a value below the trigger level ( ...
Page 73
... Reset Flags. 6.8.8 Internal Voltage Reference Atmel ATA6612/ATA6613 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 6.8.8.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
Page 74
... In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the sys- tem doesn't restart the counter, an interrupt or system reset will be issued. Atmel ATA6612/ATA6613 74 Internal Voltage Reference Characteristics ...
Page 75
... WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. as desired, but with the WDCE bit cleared. This must be done in one operation. Atmel ATA6612/ATA6613 75 ...
Page 76
... Assembly Code Example C Code Example Note: Note: Atmel ATA6612/ATA6613 76 (1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR r16, (0xff & (0<<WDRF)) andi MCUSR, r16 out ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCSR r16, (1< ...
Page 77
... WDT_Prescaler_Change(void) { __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); } 1. The example code assumes that the part specific header file is included. Atmel ATA6612/ATA6613 77 ...
Page 78
... Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Atmel ATA6612/ATA6613 78 Bit 7 ...
Page 79
... This section describes the specifics of the interrupt handling as performed in Atmel ATA6612/ATA6613. For a general explanation of the AVR and Interrupt Handling” on page The interrupt vectors in Atmel ATA6612 and ATA6613 are generally the same, with the follow- ing differences: • Each Interrupt Vector occupies two instruction words in ATA6613, and one instruction word in Atmel ATA6612. • ...
Page 80
... Store Program Memory Ready 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset (see “Boot Loader Support – Read-While-Write Self-Programming, Atmel ATA6612 and ATA6613” on page 284). 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section ...
Page 81
... Reset and Interrupt Vectors Placement in Atmel IVSEL Reset Address 1 0 0x000 1 1 0x000 0 0 Boot Reset Address 0 1 Boot Reset Address 1. The Boot Reset Address is shown in means unprogrammed while “ ...
Page 82
... When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel ATA6612 is: Address Labels Code .org 0x001 0x001 0x002 ... ...
Page 83
... When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel is: Address Labels Code ...
Page 84
... Store Program Memory Ready 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset (see “Boot Loader Support – Read-While-Write Self-Programming, Atmel ATA6612 and ATA6613” on page 284). 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section ...
Page 85
... SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> xxx ... ... ... ... Atmel ATA6612/ATA6613 Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; PCINT0 Handler ; PCINT1 Handler ; PCINT2 Handler ; Watchdog Timer Handler ; Timer2 Compare A Handler ; Timer2 Compare B Handler ; Timer2 Overflow Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ...
Page 86
... Reset and Interrupt Vector Addresses in ATA6613 is: Address Labels Code .org 0x0002 0x0002 0x0004 ... 0x0032 ; .org 0x1C00 0x1C00 0x1C01 0x1C02 0x1C03 0x1C04 0x1C05 Atmel ATA6612/ATA6613 86 RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx jmp EXT_INT0 jmp EXT_INT1 ...
Page 87
... Moving Interrupts Between Application and Boot Space, Atmel ATA6612 and ATA6613 The MCU Control Register controls the placement of the Interrupt Vector table. 6.9.2.2 MCU Control Register – MCUCR Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory ...
Page 88
... The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resis- tance. All I/O pins have protection diodes to both V on page Atmel ATA6612/ATA6613 88 Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< ...
Page 89
... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 9111H–AUTO–01/11 Pxn C pin 107. 95. Refer to the individual module sections for a full description of the Atmel ATA6612/ATA6613 R pu Logic See Figure "General Digital I/O" for Details “Register Description for I/O Ports” on “ ...
Page 90
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). Atmel ATA6612/ATA6613 90 (1) Pxn ...
Page 91
... Input 1 1 Input 0 X Output 1 X Output Figure 6-23 on page shows a timing diagram of the synchronization when reading an externally applied Atmel ATA6612/ATA6613 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...
Page 92
... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 6-25. Synchronization when Reading a Software Assigned Pin Value Atmel ATA6612/ATA6613 92 SYSTEM CLK INSTRUCTIONS ...
Page 93
... For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Atmel ATA6612/ATA6613 93 ...
Page 94
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V rents if the pin is accidentally configured as an output. Atmel ATA6612/ATA6613 94 Figure 6-23 on page 90, the digital input signal can be clamped to ground at the “ ...
Page 95
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Atmel ATA6612/ATA6613 Figure 6-23 on page 90 ® ...
Page 96
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for fur- ther details. Atmel ATA6612/ATA6613 96 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables ...
Page 97
... OC1B (Timer/Counter1 Output Compare Match B Output) PCINT2 (Pin Change Interrupt 2) OC1A (Timer/Counter1 Output Compare Match A Output) PB1 PCINT1 (Pin Change Interrupt 1) ICP1 (Timer/Counter1 Input Capture Input) PB0 CLKO (Divided System Clock Output) PCINT0 (Pin Change Interrupt 0) Atmel ATA6612/ATA6613 PUD – – IVSEL ...
Page 98
... SPI is enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB4 bit. PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source. Atmel ATA6612/ATA6613 98 9111H–AUTO–01/11 ...
Page 99
... B to the overriding signals shown in SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUT- PUT and SPI SLAVE INPUT. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 and Table 6-34 on page 100 relate the alternate functions of Port Figure 6-26 on page 95 ...
Page 100
... AIO Notes: Table 6-34. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Atmel ATA6612/ATA6613 100 Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ PB6/XTAL1/ (1) TOSC2/PCINT7 TOSC1/PCINT6 INTRC • EXTCK+ INTRC + AS2 AS2 0 0 INTRC • EXTCK+ INTRC + AS2 ...
Page 101
... ADC3 (ADC Input Channel 3) PC3 PCINT11 (Pin Change Interrupt 11) ADC2 (ADC Input Channel 2) PC2 PCINT10 (Pin Change Interrupt 10) ADC1 (ADC Input Channel 1) PC1 PCINT9 (Pin Change Interrupt 9) ADC0 (ADC Input Channel 0) PC0 PCINT8 (Pin Change Interrupt 8) Atmel ATA6612/ATA6613 Table 6-35. 101 ...
Page 102
... ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses ana- log power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source. Atmel ATA6612/ATA6613 102 9111H–AUTO–01/11 ...
Page 103
... PCINT11 • PCIE1 + PCINT10 • PCIE1 + ADC3D ADC2D PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT11 INPUT PCINT10 INPUT ADC3 INPUT ADC2 INPUT Atmel ATA6612/ATA6613 (1) PC4/SDA/ADC4/PCINT12 TWEN PORTC4 • PUD TWEN SDA_OUT TWEN 0 PCINT12 • PCIE1 + ADC4D PCINT12 • PCIE1 PCINT12 INPUT ...
Page 104
... The OC0A pin is also the output pin for the PWM mode timer function. PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt source. Atmel ATA6612/ATA6613 104 Port D Pins Alternate Functions Port Pin ...
Page 105
... DDD0. When the USART forces this pin input, the pull-up can still be controlled by the PORTD0 bit. PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 105 ...
Page 106
... Table 6-40. Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Atmel ATA6612/ATA6613 106 and Table 6-40 relate the alternate functions of Port D to the overriding signals Figure 6-26 on page 95. Overriding Signals for Alternate Functions PD7..PD4 PD7/AIN1 PD6/AIN0/ /PCINT23 OC0A/PCINT22 0 ...
Page 107
... R/W R Bit – DDC6 DDC5 R R/W R Bit – PINC6 PINC5 N/A N/A Bit PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R Atmel ATA6612/ATA6613 R/W R/W R/W R DDB4 DDB3 DDB2 DDB1 R/W R/W R/W R PINB4 PINB3 PINB2 PINB1 N/A N/A ...
Page 108
... MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in Atmel ATA6612/ATA6613 108 Bit 7 ...
Page 109
... Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the Atmel zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set ...
Page 110
... Read/Write Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero. • Bit 1 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one) ...
Page 111
... Read/Write Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero. • Bit 2 - PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector ...
Page 112
... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is an unused bit in the Atmel • Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin ...
Page 113
... Control Logic clk Direction TN Prescaler TOP BOTTOM = = 0 OCnA (Int.Req.) Fixed OCnB TOP (Int.Req.) Value TCCRnB Atmel ATA6612/ATA6613 Figure 6-27. The device-spe- “8-bit Timer/Counter Register Description” must be written to zero to TOVn (Int.Req.) TOSC1 T/C Oscillator TOSC2 clk I/O Waveform OCnA Generation Waveform ...
Page 114
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler (see Atmel ATA6612/ATA6613 114 Table 6-43 are also used extensively throughout the document. ...
Page 115
... Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). ). clk present or not. A CPU write overrides (has priority over) all T0 “Modes of Operation” on page Atmel ATA6612/ATA6613 TOVn (Int.Req.) Clock Select count Edge Detector clk clear ...
Page 116
... OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated real com- pare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). Atmel ATA6612/ATA6613 116 shows a block diagram of the Output Compare unit. DATA BUS ...
Page 117
... OC0x state, the reference is for the internal OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. Figure 6-30. Compare Match Output Unit, Schematic 9111H–AUTO–01/11 COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O Atmel ATA6612/ATA6613 Figure 6- OCnx DDR shows a sim- OCnx Pin 117 ...
Page 118
... The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Atmel ATA6612/ATA6613 118 “8-bit Timer/Counter Register Description” on page Table 6-44 on page 125, and for phase correct PWM refer to “ ...
Page 119
... MAX to 0x00. 9111H–AUTO–01/11 TCNTn OCn (Toggle Period /2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the follow- f clk_I/O = ------------------------------------------------------ - N OCRnx Atmel ATA6612/ATA6613 Figure 6-31. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 OC0 119 ...
Page 120
... OC0x Register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). Atmel ATA6612/ATA6613 120 Figure 6-32. The TCNT0 value is in the timing diagram shown as a ...
Page 121
... PWM outputs. The small horizontal line marks on the TCNT0 slopes represent com- pare matches between OCR0x and TCNT0. 9111H–AUTO–01/11 f clk_I/O = -------------------- - N 256 Figure 6-33 on page 122. The TCNT0 value is in the timing diagram shown as a Atmel ATA6612/ATA6613 = f /2 when OCR0A is set to zero. OC0 clk_I/O 121 ...
Page 122
... PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. Atmel ATA6612/ATA6613 122 1 ...
Page 123
... MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. clk I/O clk TN /8) I/O MAX - 1 TOVn Atmel ATA6612/ATA6613 OCnx has a transition from high to low Figure 6-33 on page 122. When the OCR0A ) is therefore shown MAX BOTTOM /8) clk_I/O MAX BOTTOM ...
Page 124
... Figure 6-37 PWM mode where OCR0A is TOP. Figure 6-37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with (clk TCNTn OCRnx OCFnx Atmel ATA6612/ATA6613 124 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC clk I/O clk Tn /8) ...
Page 125
... Set OC0A on Compare Match, clear OC0A at TOP 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See 120 for more details. Atmel ATA6612/ATA6613 – – ...
Page 126
... WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 6-47. COM0B1 Table 6-48 mode. Table 6-48. COM0B1 Note: Atmel ATA6612/ATA6613 126 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 0 Normal port operation, OC0A disconnected ...
Page 127
... Table 6-49. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the Atmel zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what ...
Page 128
... A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the Atmel zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • ...
Page 129
... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge. Bit R/W R/W R Bit R/W R/W R Bit R/W R/W R Atmel ATA6612/ATA6613 TCNT0[7:0] R/W R/W R/W R OCR0A[7:0] R/W R/W R/W R OCR0B[7:0] R/W R/W R/W R/W ...
Page 130
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the Atmel ATA6612/ATA6613 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 131
... The T1/T0 pin is sampled once every system clock cycle by the pin synchroniza- T0 shows a functional equivalent block diagram of the T1/T0 synchroni- ). The latch is transparent in the high period of the internal system clock. clk I/O T1 Atmel ATA6612/ATA6613 /clk pulse for each positive (CSn2 negative T 0 Table 6-50 on 127. ...
Page 132
... Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 6-39. Prescaler for Timer/Counter0 and Timer/Counter1 PSRSYNC CS10 CS11 CS12 Note: Atmel ATA6612/ATA6613 132 clk I/O Synchronization < ...
Page 133
... The device-specific I/O Register and bit locations are listed in the ter Description” on page The PRTIM1 bit in enable Timer/Counter1 module. 9111H–AUTO–01/11 Bit TSM – – R 155. “Power Reduction Register - PRR” on page 66 Atmel ATA6612/ATA6613 – – – PSRASY R Figure 6-40 on page “16-bit Timer/Counter Regis- must be written to zero to ...
Page 134
... T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk Atmel ATA6612/ATA6613 134 Count Clear ...
Page 135
... OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 142. The compare match event will also set the Com- 262). The Input Capture unit includes a digital filtering unit General Counter Definitions The counter reaches the BOTTOM when it becomes 0x0000 ...
Page 136
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Atmel ATA6612/ATA6613 136 (1) ... ...
Page 137
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Atmel ATA6612/ATA6613 137 ...
Page 138
... If writing to more than one 16-bit register where the high byte is the same for all registers writ- ten, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Atmel ATA6612/ATA6613 138 (1) ...
Page 139
... TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). ). The clk present or not. A CPU write overrides (has priority over) all T 1 Atmel ATA6612/ATA6613 TOVn (Int.Req.) Clock Select Count Edge Detector clk Clear Tn Control Logic ...
Page 140
... Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Atmel ATA6612/ATA6613 140 DATA BUS (8-bit) TEMP (8-bit) ...
Page 141
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 135. “Accessing 16-bit Regis- Figure 6-38 on page 132) ...
Page 142
... Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 6-43. Output Compare Unit, Block Diagram Atmel ATA6612/ATA6613 142 “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register ...
Page 143
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 “Accessing 16-bit Registers” on page 135. 143 ...
Page 144
... The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation (see The COM1x1:0 bits have no effect on the Input Capture unit. Atmel ATA6612/ATA6613 144 COMnx1 Waveform ...
Page 145
... The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 Table 6-53 on page 155, and for phase correct and phase and frequency correct PWM refer to 156. ...
Page 146
... OCnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. Atmel ATA6612/ATA6613 146 TCNTn OCnA (Toggle) 1 ...
Page 147
... Figure 6-46. Fast PWM Mode, Timing Diagram 9111H–AUTO–01/11 TOP log + 1 = ---------------------------------- - log 2 TCNTn OCnx OCnx Period Atmel ATA6612/ATA6613 OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 Figure 147 ...
Page 148
... PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits). Atmel ATA6612/ATA6613 148 f clk_I/O ...
Page 149
... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 9111H–AUTO–01/ TOP log ---------------------------------- - log 2 150. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define Atmel ATA6612/ATA6613 /2 when OCR1A is set to zero (0x0000). This fea- clk_I/O Figure 6-47 on 149 ...
Page 150
... The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the coun- ter decrements. Atmel ATA6612/ATA6613 150 TCNTn OCnx ...
Page 151
... TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 9111H–AUTO–01/11 f clk_I/O = --------------------------------- N TOP 2 and Figure 6-48 on page 152). TOP log + 1 = ---------------------------------- - log 2 Figure 6-48 on page Atmel ATA6612/ATA6613 152. The figure shows phase Figure 151 ...
Page 152
... OCR1x and TCNT1 when the counter decrements. The PWM frequency for the out- put when using phase and frequency correct PWM can be calculated by the following equation: f OCnxPFCPWM The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). Atmel ATA6612/ATA6613 152 TCNTn OCnx OCnx 1 ...
Page 153
... OCFnx shows the same timing data, but with the prescaler enabled. clk I/O clkTn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Atmel ATA6612/ATA6613 ) is therefore shown shows a timing diagram for the setting of OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) clk_I/O ...
Page 154
... ICFn (if used (Update at TOP) Figure 6-52 Figure 6-52. Timer/Counter Timing Diagram, with Prescaler (f (CTC and FPWM) (PC and PFC PWM) and ICFn (if used (Update at TOP) Atmel ATA6612/ATA6613 154 shows the count sequence close to TOP in various modes. When using phase clk I/O clk Tn (clk ...
Page 155
... Compare Output Mode, Fast PWM COM1A0/COM1B0 special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See Mode” on page 147 for more details. Atmel ATA6612/ATA6613 – – WGM11 R R ...
Page 156
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see Atmel ATA6612/ATA6613 156 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase Compare Output Mode, Phase Correct and Phase and Frequency Correct ...
Page 157
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM Bit ICNC1 ICES1 – R/W R Atmel ATA6612/ATA6613 Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICR1 BOTTOM OCR1A BOTTOM ICR1 ...
Page 158
... COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. Atmel ATA6612/ATA6613 158 and Figure 6-50 on page ...
Page 159
... High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers (see 9111H–AUTO–01/11 Bit R/W R/W R 135. Bit R/W R/W R Bit R/W R/W R “Accessing 16-bit Registers” on page Atmel ATA6612/ATA6613 TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] ...
Page 160
... TIFR1, is set. • Bit 4, 3 – Res: Reserved Bits These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero. • Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob- ally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled ...
Page 161
... ICF1 can be cleared by writing a logic one to its bit location. • Bit 4, 3 – Res: Reserved Bits These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero. • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out- put Compare Register B (OCR1B) ...
Page 162
... I/O Register and bit locations are listed in the on page The PRTIM2 bit in enable Timer/Counter2 module. Figure 6-53. 8-bit Timer/Counter Block Diagram Timer/Counter TCNTn = OCRnA = OCRnB TCCRnA Atmel ATA6612/ATA6613 162 174. “Power Reduction Register - PRR” on page 66 Count Clear Control Logic clk Direction TN Prescaler TOP ...
Page 163
... AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation (see sources and prescaler, see 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 ). T2 “Output Compare Unit” on page 165 The counter reaches the BOTTOM when it becomes zero (0x00). ...
Page 164
... OC2B. For more details about advanced counting sequences and waveform generation (see The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. Atmel ATA6612/ATA6613 164 shows a block diagram of the counter and its surrounding environment. DATA BUS ...
Page 165
... COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 9111H–AUTO–01/11 168). shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator) top bottom Waveform Generator FOCn WGMn1:0 Atmel ATA6612/ATA6613 TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 “Modes of 165 ...
Page 166
... I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. Atmel ATA6612/ATA6613 166 Figure 6-56 on page 167 ...
Page 167
... For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 9111H–AUTO–01/11 COMnx1 Waveform COMnx0 Generator FOCnx clk I/O “8-bit Timer/Counter Register Description” on page Table 6-61 on page 175, and for phase correct PWM refer to Atmel ATA6612/ATA6613 OCnx PORT D Q DDR 174). ...
Page 168
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 6-57. CTC Mode, Timing Diagram Atmel ATA6612/ATA6613 168 “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ...
Page 169
... OCR2x and TCNT2. 9111H–AUTO–01/11 /2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the follow- f clk_I/O = ------------------------------------------------------ - N OCRnx Figure 6-58 on page Atmel ATA6612/ATA6613 Flag is set in the same timer clock cycle that TOV2 170. The TCNT2 value is in the timing diagram = OC2A 169 ...
Page 170
... OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The wave- form generated will have a maximum frequency of f This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. Atmel ATA6612/ATA6613 170 1 2 ...
Page 171
... The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOT- TOM value. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 Figure 6-59. The TCNT2 value is in the timing diagram shown as a histogram for 1 ...
Page 172
... Timer/Counter Oscillator clock. The figures include information on when Inter- rupt Flags are set. figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 6-60. Timer/Counter Timing Diagram, no Prescaling (clk TCNTn Atmel ATA6612/ATA6613 172 f clk_I/O = -------------------- - N ...
Page 173
... Tn /8) I/O OCRnx - 1 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Prescaler (f /8) clk_I/O clk I/O clkTN /8) I/O TOP - 1 (CTC) Atmel ATA6612/ATA6613 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 BOTTOM + 1 173 ...
Page 174
... When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 6-58. COM2A1 Table 6-59 mode. Table 6-59. COM2A1 Note: Atmel ATA6612/ATA6613 174 Bit COM2A1 COM2A0 COM2B1 COM2B0 R/W R/W R/W ...
Page 175
... A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See on page 171 for more details. Atmel ATA6612/ATA6613 (1) “Phase Correct PWM Mode” shows the COM2B1:0 bit functionality when the (1) “ ...
Page 176
... Table 6-63. COM2B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the Atmel zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...
Page 177
... A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the Atmel zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in • ...
Page 178
... Output Compare Register B – OCR2B Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. Atmel ATA6612/ATA6613 178 Clock Select Bit Description CS21 CS20 0 ...
Page 179
... Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. 9111H–AUTO–01/11 Bit – – – Bit – – – Atmel ATA6612/ATA6613 – – OCIE2B OCIE2A R R R/W R – – OCF2B OCF2A R R R/W R/W 0 ...
Page 180
... If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: Atmel ATA6612/ATA6613 180 a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. ...
Page 181
... Enter Power-save or ADC Noise Reduction mode. a. Write any value to either of the registers OCR2x or TCCR2x. b. Wait for the corresponding Update Busy Flag to be cleared. c. Read TCNT2 – EXCLK AS2 TCN2UB R R/W R Atmel ATA6612/ATA6613 ) again becomes active, TCNT2 will read as the I OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR R 0 ...
Page 182
... The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are differ- ent. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. Atmel ATA6612/ATA6613 182 9111H–AUTO–01/11 ...
Page 183
... By setting the AS2 bit in ASSR, Timer/Counter2 is asynchro- IO /128, clk /256, and clk /1024. Additionally, clk T2S T2S TSM – – R Atmel ATA6612/ATA6613 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the T2S T2S /8, clk T2S T2S as well as 0 (stop) may be T2S – ...
Page 184
... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel Atmel • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • ...
Page 185
... SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. 9111H–AUTO–01/11 MASTER LSB MSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR Atmel ATA6612/ATA6613 Figure MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SHIFT ENABLE ...
Page 186
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Atmel ATA6612/ATA6613 186 Table 6-66. For more details on automatic port overrides, refer to 95 ...
Page 187
... Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. The example code assumes that the part specific header file is included. Atmel ATA6612/ATA6613 187 ...
Page 188
... The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: Atmel ATA6612/ATA6613 188 (1) ; Set MISO output, all others input r17,(1<<DD_MISO) ldi DDR_SPI,r17 out ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ...
Page 189
... When the DORD bit is written to zero, the MSB of the data word is transmitted first. 9111H–AUTO–01/11 of the SPI becoming a Slave, the MOSI and SCK pins become inputs. SREG is set, the interrupt routine will be executed SPIE SPE DORD R/W R/W R Atmel ATA6612/ATA6613 MSTR CPOL CPHA SPR1 R/W R/W R/W R ...
Page 190
... Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f Table 6-69. Atmel ATA6612/ATA6613 190 Figure 6-67 CPOL Functionality CPOL ...
Page 191
... WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the Atmel zero. • Bit 0 – SPI2X: Double SPI Speed Bit ...
Page 192
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum- marizing Table 6-70. Figure 6-67. SPI Transfer Format with CPHA = 0 Figure 6-68. SPI Transfer Format with CPHA = 1 Atmel ATA6612/ATA6613 192 and Figure 6-68. Data bits are shifted out and latched in on opposite edges of the ...
Page 193
... Overview A simplified block diagram of the USART Transmitter is shown in CPU accessible I/O Registers and I/O pins are shown in bold. 9111H–AUTO–01/11 Atmel ATA6612/ATA6613 “USART in SPI Mode” on page “Power Reduction Register - PRR” on page Figure 6-69 on page 220. 194. ...
Page 194
... Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame for- mats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. Atmel ATA6612/ATA6613 194 (1) ...
Page 195
... Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Atmel ATA6612/ATA6613 U2Xn / DDR_XCKn 0 1 Figure 6-70 ...
Page 196
... For the Transmitter, there are no downsides. Atmel ATA6612/ATA6613 196 contains equations for calculating the baud rate (in bits per second) and for calcu- ...
Page 197
... Figure 6-70 on page 195 f OSC ---------- - 4 depends on the stability of the system clock source therefore recommended osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 6-71 Atmel ATA6612/ATA6613 for details. Sample Sample shows, when UCPOLn is zero the data will be 197 ...
Page 198
... USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. Atmel ATA6612/ATA6613 198 Figure 6-72 illustrates the possible combinations of the frame formats. Bits ...
Page 199
... For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. 9111H–AUTO–01/ even n 1 – odd n 1 – P Parity bit using even parity even odd P Parity bit using odd parity d Data bit n of the character n Atmel ATA6612/ATA6613 199 ...
Page 200
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. Atmel ATA6612/ATA6613 200 (1) ; Set baud rate ...