ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 17

MCU AVR 8K FLASH 16MHZ 28-PDIP

ATMEGA8A-PU

Manufacturer Part Number
ATMEGA8A-PU
Description
MCU AVR 8K FLASH 16MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8A-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
7.3.1
8159D–AVR–02/11
Data Memory Access Times
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 7-3.
Data Memory Map
I/O Registers
On-chip Data SRAM Access Cycles
Register File
Address
clk
R29
R30
$3D
R31
$3E
$3F
Data
Data
$00
$01
$02
R0
R1
R2
WR
...
...
CPU
RD
Compute Address
T1
Memory Vccess Instruction
Address Valid
CPU
T2
cycles as described in
Next Instruction
Data Address Space
T3
Internal SRAM
$001D
$005D
$001E
$005E
$005F
$045E
$045F
$0000
$0001
$0002
$001F
$0020
$0021
$0022
$0060
$0061
...
...
...
ATmega8A
Figure
7-3.
17

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