ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 186

MCU AVR 8K FLASH 16MHZ 28-PDIP

ATMEGA8A-PU

Manufacturer Part Number
ATMEGA8A-PU
Description
MCU AVR 8K FLASH 16MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8A-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
20.6.5
8159D–AVR–02/11
Slave Transmitter Mode
Figure 20-15. Formats and States in the Slave Receiver Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see
are zero or are masked to zero.
Figure 20-16. Data Transfer in Slave Transmitter Mode
Figure
Reception of the own
slave address and one or
more data bytes. All are
acknowledged
Last data byte received
is not acknowledged
Arbitration lost as master
and addressed as slave
Reception of the general call
address and one or more data
bytes
Last data byte received is
not acknowledged
Arbitration lost as master and
addressed as slave by general call
SDA
SCL
20-16). All the status codes mentioned in this section assume that the prescaler bits
From master to slave
From slave to master
TRANSMITTER
Device 1
S
SLAVE
SLA
General Call
Device 2
RECEIVER
MASTER
W
DATA
$60
$68
$70
$78
Device 3
A
A
A
A
n
A
........
DATA
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Device n
$80
$90
V
A
A
CC
DATA
DATA
R1
ATmega8A
$80
$88
$90
$98
A
A
A
A
R2
P or S
P or S
P or S
P or S
$A0
$A0
186

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