ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 52

• Manufacturer Part Number: ATMEGA8A-PU
• Description: MCU AVR 8K FLASH 16MHZ 28-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.2
8159D–AVR–02/11
Reading the Pin Value
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
W h e n s w i t c h i n g b e t w e e n t r i - s t a t e ( { D D x n , P O R T x n } = 0 b 0 0 ) a n d o u t p u t h i g h
( { D D x n , P O R T x n } = 0 b 1 1 ) , a n i n t e r m e d i a t e s t a t e w i t h e i t h e r p u l l - u p e n a b l e d
({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the
pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the
SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
m u s t u s e e i th e r th e tr i - s t at e ({D D x n, P O R T x n } = 0 b 00 ) o r t h e ou t pu t h i g h s ta t e
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 12-1
Table 12-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register Bit. As shown in
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay.
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
DDxn
0
0
0
1
1
PORTxn
summarizes the control signals for the pin value.
0
1
1
0
1
Port Pin Configurations
(in SFIOR)
PUD
X
X
X
0
1
Figure
Output
Output
Input
Input
Input
I/O
12-2, the PINxn Register bit and the preceding latch con-
pd,max
Pull-up
Yes
No
No
No
No
and t
pd,min
Comment
Tri-state (Hi-Z)
Pxn will source current if external pulled
low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
, respectively.
Figure 12-3
ATmega8A
shows a timing dia-
52