ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 62

• Manufacturer Part Number: ATMEGA8A-PU
• Description: MCU AVR 8K FLASH 16MHZ 28-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8159D–AVR–02/11
• ADC2 – Port C, Bit 2
PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog
power.
• ADC1 – Port C, Bit 1
PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog
power.
• ADC0 – Port C, Bit 0
PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog
power.
Table 12-6
shown in
Table 12-6.
Table 12-7.
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins
Figure 12-5 on page
PC4 and PC5. This is not shown in the figure. In addition, spike filters are connected between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
and
Overriding Signals for Alternate Functions in PC6:PC4
Overriding Signals for Alternate Functions in PC3:PC0
Table 12-7
PC6/RESET
RSTDISBL
1
RSTDISBL
0
0
0
RSTDISBL
0
–
RESET INPUT
PC3/ADC3
0
0
0
0
0
0
0
0
–
ADC3 INPUT
relate the alternate functions of Port C to the overriding signals
56.
PC5/SCL/ADC5
TWEN
PORTC5 • PUD
TWEN
SCL_OUT
TWEN
0
0
0
–
ADC5 INPUT / SCL INPUT
PC2/ADC2
0
0
0
0
0
0
0
0
–
ADC2 INPUT
PC1/ADC1
0
0
0
0
0
0
0
–
ADC1 INPUT
0
PC4/SDA/ADC4
TWEN
PORTC4 • PUD
TWEN
SDA_OUT
TWEN
0
0
0
–
ADC4 INPUT / SDA INPUT
(1)
ATmega8A
PC0/ADC0
0
0
0
0
0
0
0
0
–
ADC0 INPUT
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