ATMEGA324PA-PU Atmel, ATMEGA324PA-PU Datasheet

ATMEGA324PA-PU

Manufacturer Part Number

ATMEGA324PA-PU

Description

MCU AVR 32KB FLASH 40PDIP

Manufacturer

Atmel

Series

AVR® ATmegar

Datasheets

1.ATMEGA644PA-PU.pdf (581 pages)

2.ATMEGA644PA-PU.pdf (32 pages)

3.ATMEGA164PA-AN.pdf (30 pages)

Specifications of ATMEGA324PA-PU

Core Processor

AVR

Core Size

8-Bit

Speed

20MHz

Connectivity

I²C, SPI, UART/USART

Peripherals

Brown-out Detect/Reset, POR, PWM, WDT

Number Of I /o

Program Memory Size

32KB (16K x 16)

Program Memory Type

FLASH

Eeprom Size

1K x 8

Ram Size

2K x 8

Voltage - Supply (vcc/vdd)

1.8 V ~ 5.5 V

Data Converters

A/D 8x10b

Oscillator Type

Internal

Operating Temperature

-40°C ~ 85°C

Package / Case

40-DIP (0.600", 15.24mm)

Controller Family/series

AVR MEGA

No. Of I/o's

Eeprom Memory Size

1KB

Ram Memory Size

2KB

Cpu Speed

20MHz

Rohs Compliant

Yes

For Use With

ATSTK600 - DEV KIT FOR AVR/AVR32

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Features

•

Note:

High-performance, Low-power AVR

Advanced RISC Architecture

High Endurance Non-volatile Memory segments

JTAG (IEEE std. 1149.1 Compliant) Interface

Peripheral Features

Special Microcontroller Features

I/O and Packages

Operating Voltages

Speed Grades for ATmega164PA/324PA/644PA/1284P

Power Consumption at 1 MHz, 1.8V, 25°C

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

– 16/32/64/128K Bytes of In-System Self-programmable Flash program memory

– 512B/1K/2K/4K Bytes EEPROM (ATmega164PA/324PA/644PA/1284P)

– 1/2/4/16K Bytes Internal SRAM (ATmega164PA/324PA/644PA/1284P)

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C

– Optional Boot Code Section with Independent Lock Bits

– Programming Lock for Software Security

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel, 10-bit ADC

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

– 1.8 - 5.5V

– 0 - 20MHz @ 1.8 - 5.5V

– Active: 0.4 mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32 kHz RTC)

(ATmega164PA/324PA/644PA/1284P)

Extended Standby

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Differential mode with selectable gain at 1x, 10x or 200x

1. See

”Data Retention” on page 9

8-bit Microcontroller

for details.

(1)

8-bit

Microcontroller

with

16/32/64/128K

Bytes In-System

Programmable

Flash

ATmega164PA

ATmega324PA

ATmega644PA

ATmega1284P

Summary

Rev. 8152GS–AVR–11/09

Related parts for ATMEGA324PA-PU

ATMEGA324PA-PU Summary of contents

Page 1

... Power-down Mode: 0.1µA – Power-save Mode: 0.6µA (Including 32 kHz RTC) Note: 1. See ”Data Retention” on page 9 ® 8-bit Microcontroller (1) for details. 8-bit Microcontroller with 16/32/64/128K Bytes In-System Programmable Flash ATmega164PA ATmega324PA ATmega644PA ATmega1284P Summary Rev. 8152GS–AVR–11/09 ...

Page 2

Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164PA/324PA/644PA/1284P Figure 1-1. Note: 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P Pinout (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 ...

Page 3

Pinout - DRQFN for ATmega164PA/324PA/644PA Figure 1- Table 1- 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P DRQFN - Pinout Top view B1 B15 B2 B14 B3 B13 ...

Page 4

Pinout - VFBGA for ATmega164PA/324PA/644PA Figure 1- Table 1- 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P VFBGA - Pinout Top view BGA - ...

Page 5

Overview The ATmega164PA/324PA/644PA/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164PA/324PA/644PA/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 6

... Atmel ATmega164PA/324PA/644PA/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164PA/324PA/644PA/1284P AVR is supported with a full suite of program and sys debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Comparison Between ATmega164PA, ATmega324PA, ATmega644PA and ATmega1284P Table 2-1. Device ATmega164PA ATmega324PA ATmega644PA ATmega1284P 8152GS– ...

Page 7

Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected ...

Page 8

RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characteristics” on page 2.3.8 XTAL1 ...

Page 9

... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent ...

Page 10

Register Summary Address Name Bit 7 (0xFF) Reserved - (0xFE) Reserved - (0xFD) Reserved - (0xFC) Reserved - (0xFB) Reserved - (0xFA) Reserved - (0xF9) Reserved - (0xF8) Reserved - (0xF7) Reserved - (0xF6) Reserved - (0xF5) Reserved - ...

Page 11

Address Name Bit 7 (0xC0) UCSR0A RXC0 (0xBF) Reserved - (0xBE) Reserved - (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved - (0xB6) ASSR - (0xB5) Reserved - (0xB4) OCR2B ...

Page 12

Address Name Bit 7 (0x7E) DIDR0 ADC7D (0x7D) Reserved - (0x7C) ADMUX REFS1 (0x7B) ADCSRB - (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved - (0x76) Reserved - (0x75) Reserved - (0x74) Reserved - (0x73) PCMSK3 PCINT31 (0x72) Reserved ...

Page 13

Address Name Bit 7 0x1C (0x3C) EIFR - 0x1B (0x3B) PCIFR - 0x1A (0x3A) Reserved - 0x19 (0x39) Reserved - 0x18 (0x38) Reserved - 0x17 (0x37) TIFR2 - 0x16 (0x36) TIFR1 - 0x15 (0x35) TIFR0 - 0x14 (0x34) Reserved - ...

Page 14

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 15

Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...

Page 16

Mnemonics Operands PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P Description STACK ← ← STACK (see specific descr. for ...

Page 17

... Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. ...

Page 18

... Staggered 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN) 49C2 49-ball Array) 0.65 mm Pitch mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P (2) Ordering Code Package ATmega324PA-AU 44A ATmega324PA-PU 40P6 ATmega324PA-MU 44M1 (4) ATmega324PA-MCH 44MC ATmega324PA-CU 49C2 328. ...

Page 19

Page 20

Page 21

Packaging Information 9.1 44A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...

Page 22

A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm ...

Page 23

... D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P E Pin #1 Corner Pin #1 Option A 1 Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0 ...

Page 24

... Pin A19 B16 eR A18 B15 D2 B11 A13 B10 A12 L BOTTOM VIEW 1. The terminal # Laser-marked Feature. Note: Package Drawing Contact: packagedrawings@atmel.com 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P E TOP VIEW eT/2 A24 B20 0.40 R0. TITLE 44MC, 44QFN (2-Row Staggered 1.00 mm Body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package ...

Page 25

... A1 BALL BALL CORNER b Package Drawing Contact: packagedrawings@atmel.com 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P E D TOP VIEW 0.35 ± 0.05 Ø e BOTTOM VIEW TITLE 49C2, 49-ball ( Array), 0.65 mm Pitch, 5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 0. SIDE VIEW ...

Page 26

... Errata 10.1 ATmega164PA Rev known Errata. 10.2 ATmega324PA Rev known Errata. 10.3 ATmega644PA Rev known Errata. 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P 26 ...

Page 27

Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. 8152G- 11/ 11.2 Rev. 8152F- ...

Page 28

... Inserted “ATmega644PA” Ordering Information. Updated ”Errata” on page 430. Updated ”Features” on page 1 by inserting ATmega324PA device and updated the whole datasheet accordingly. Updated ”Overview” on page 5. Inserted ”Comparison Between ATmega164PA and ATmega324PA” on page Updated all resgister description in ”AVR CPU Core” on page Updated “ ...

Page 29

Rev. 8152A- 11/ Initial revision (Based on the ATmega164P/324P/644P datasheet 8011K-AVR-09/08). Changes done compared to ATmega164P/324P/644P datasheet 8011K-AVR-09/08: –New graphics in ”Typical Characteristics” on page 337 –New ”Ordering Information” on page 395 ...

Page 30

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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