ATMEGA324PA-PU Atmel, ATMEGA324PA-PU Datasheet - Page 156

MCU AVR 32KB FLASH 40PDIP

ATMEGA324PA-PU

Manufacturer Part Number
ATMEGA324PA-PU
Description
MCU AVR 32KB FLASH 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA324PA-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16.11.2
8272A–AVR–01/10
TCCR2B – Timer/Counter Control Register B
Table 16-7
rect PWM mode.
Table 16-7.
Note:
• Bits 3:2 – Res: Reserved Bits
These bits are reserved bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
Table 16-8.
Notes:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
Mode
COM2B1
0
1
2
3
4
5
6
7
0
0
1
1
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
1. MAX= 0xFF
2. BOTTOM= 0x00
WGM2
pare Match is ignored, but the set or clear is done at TOP. See
page 148
shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
0
0
0
0
1
1
1
1
Compare Output Mode, Phase Correct PWM Mode
Waveform Generation Mode Bit Description
COM2B0
7
for more details.
WGM1
0
1
0
1
0
0
1
1
0
0
1
1
6
Description
Normal port operation, OC2B disconnected.
Reserved
Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.
Set OC2B on Compare Match when up-counting. Clear OC2B on
Compare Match when down-counting.
WGM0
Table
0
1
0
1
0
1
0
1
5
16-8. Modes of operation supported by the Timer/Counter
Timer/Counter
Mode of
Operation
Normal
PWM, Phase
Correct
CTC
Fast PWM
Reserved
PWM, Phase
Correct
Reserved
Fast PWM
”Modes of Operation” on page
4
3
OCRA
OCRA
OCRA
0xFF
0xFF
0xFF
TOP
2
(1)
”Phase Correct PWM Mode” on
Update of
Immediate
Immediate
BOTTOM
BOTTOM
OCRx at
1
TOP
TOP
145).
0
Set on
TOV Flag
BOTTOM
BOTTOM
MAX
MAX
MAX
TOP
(1)(2)
156

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