ATMEGA324PA-PU Atmel, ATMEGA324PA-PU Datasheet - Page 192

MCU AVR 32KB FLASH 40PDIP

ATMEGA324PA-PU

Manufacturer Part Number
ATMEGA324PA-PU
Description
MCU AVR 32KB FLASH 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA324PA-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
18.11.4
8272A–AVR–01/10
UCSRnC – USART Control and Status Register n C
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in
Table 18-4.
Note:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
Read/Write
Initial Value
UMSELn1
1. See
0
0
1
1
operation
UMSELn1
UMSELn Bits Settings
R/W
”USART in SPI Mode” on page 199
7
0
UMSELn0
R/W
6
0
UMSELn0
0
1
0
1
UPMn1
R/W
5
0
UPMn0
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)
R/W
Mode
4
0
for full description of the Master SPI Mode (MSPIM)
USBSn
R/W
3
0
UCSZn1
R/W
2
1
(1)
Table
UCSZn0
R/W
1
1
18-4..
UCPOLn
R/W
0
0
UCSRnC
192

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