ATMEGA324PA-PU Atmel, ATMEGA324PA-PU Datasheet - Page 220

MCU AVR 32KB FLASH 40PDIP

ATMEGA324PA-PU

Manufacturer Part Number
ATMEGA324PA-PU
Description
MCU AVR 32KB FLASH 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA324PA-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8272A–AVR–01/10
Figure 20-11. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans-
mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will
then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the
status code in TWSR will be 0x08 (see
SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes
is detailed in
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-
ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
TWCR
value
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
Table 20-2 on page
TWINT
TWINT
TWINT
TWINT
TWINT
1
1
1
1
1
TRANSMITTER
Device 1
MASTER
TWEA
TWEA
TWEA
TWEA
TWEA
X
X
X
X
X
Device 2
RECEIVER
SLAVE
221.
TWSTA
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
0
1
Table 20-2 on page
Device 3
TWSTO
TWSTO
TWSTO
TWSTO
TWSTO
0
0
1
0
0
........
TWWC
TWWC
TWWC
TWWC
TWWC
Device n
X
X
X
X
X
221). In order to enter MT mode,
V
CC
TWEN
TWEN
TWEN
TWEN
TWEN
1
1
1
1
1
R1
R2
0
0
0
0
0
TWIE
TWIE
TWIE
TWIE
TWIE
X
X
X
X
X
220

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