ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 223

MCU AVR 16K FLASH 16MHZ 44TQFP

ATMEGA32U4-AUR

Manufacturer Part Number
ATMEGA32U4-AUR
Description
MCU AVR 16K FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA32U4-AUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Price
Part Number:
ATMEGA32U4-AUR
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10 000
20. 2-wire Serial Interface
20.1
20.2
20.2.1
7766F–AVR–11/10
Features
2-wire Serial Interface Bus Definition
TWI Terminology
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 20-1. TWI Bus Interconnection
The following definitions are frequently encountered in this section.
Table 20-1.
Term
Master
Slave
Transmitter
Receiver
Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up When AVR is in Sleep Mode
SDA
SCL
Description
The device that initiates and terminates a transmission. The Master also
generates the SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
TWI Terminology
Device 1
Device 2
Device 3
........
Device n
V
CC
ATmega16/32U4
R1
R2
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