ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 28

• Manufacturer Part Number: ATMEGA32U4-AUR
• Description: MCU AVR 16K FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.2
7766F–AVR–11/10
Clock Sources
ADC Clock – clk
PLL Prescaler Clock – clk
PLL Output Clock – clk
High-Speed Timer Clock– clk
USB Clock – clk
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The PLL requires a 8 MHz input. A prescaler allows user to use either a 8MHz or a 16MHz
source (from a crystal or an external source), using a divider (by 2) if necessary. The output of
the prescaler goes into the PLL Input multiplexer, that allows the user to select either the pres-
caler output of the System Clock Multiplexer, or the Internal 8MHz Calibrated Oscillator.
When enabled, the PLL outputs one frequency among numerous choices between 32MHz and
96 MHz. The output frequency is determined by the PLL clock register. The frequency is inde-
pendent of the power supply voltage. The PLL Output is connected to a postcaler that allows
user to generate two different frequencies (clk
each on them resulting of a selected division ratio (/1, /1.5, /2).
When enabled, the PLL outputs one frequency among numerous choices between 32MHz and
96 MHz, that goes into the PLL Postcaler. The High Speed Timer frequency input is generated
from the PLL Postcaler, that proposes /1, /1.5 and /2 ratios. That can be determined from the
PLL clock register. The High Speed Timer maximum frequency input depends on the power sup-
ply voltage and reaches its maximum of 64 MHz at 5V.
The USB hardware module needs for a 48 MHz clock. This clock is generated from the on-chip
PLL. The output of the PLL passes through the PLL Postcaler where the frequency can be either
divided by 2 or directly connected to the clk
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
USB
ADC
Device Clocking Option
Low Power Crystal Oscillator
Reserved
Low Frequency Crystal Oscillator
Reserved
Calibrated Internal RC Oscillator
External Clock
Reserved
1. For all fuses “1” means unprogrammed while “0” means programmed.
Pll
PllPresc
Device Clocking Options Select
TMR
USB
(1)
signal.
USB
and clk
TMR
) from the common PLL signal,
ATmega16/32U4
(or EXCKSEL[3:0])
1111 - 1000
0101 - 0100
CKSEL[3:0]
0111 - 0110
0011
0010
0000
0001
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