ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 143

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ATMEGA32U4-MUR

Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA32U4-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
15.4
7766F–AVR–11/10
Output Compare Unit
The comparator continuously compares TCNT4 with the Output Compare Registers (OCR4A,
OCR4B, OCR4C and OCR4D). Whenever TCNT4 equals to the Output Compare Register, the
comparator signals a match. A match will set the Output Compare Flag (OCF4A, OCF4B or
OCF4D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Com-
pare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically
cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the PWM4x, WGM40 and Compare Out-
put mode (COM4x1:0) bits. The top and bottom signals are used by the Waveform Generator for
handling the special cases of the extreme values in some modes of operation
Operation” on page
Figure 15-4. Output Compare Unit, Block Diagram
The OCR4x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal mode of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR4x Compare Registers to either top or bottom of
the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym-
metrical PWM pulses, thereby making the output glitch-free. See
During the time between the write and the update operation, a read from OCR4A, OCR4B,
OCR4C or OCR4D will read the contents of the temporary location. This means that the most
recently written value always will read out of OCR4A, OCR4B, OCR4C or OCR4D.
BOTTOM
149.).
FOCn
OCRnx
TOP
10-BIT OCRnx
Figure 15-4
Waveform Generator
=
shows a block diagram of the Output Compare unit.
8-BIT DATA BUS
(10-bit Comparator )
OCWnx
TCnH
10-BIT TCNTn
ATmega16/32U4
TCNTn
COMnX1:0
PWMnx
WGMn0
Figure 15-5
OCFnx (Int.Req.)
for an example.
(See “Modes of
143

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