ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 297

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ATMEGA32U4-MUR

Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA32U4-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
24.4.1
7766F–AVR–11/10
Differential Channels
Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 24-7. ADC Timing Diagram, Free Running Conversion
Table 24-1.
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock frequency. This synchronization is done automatically by the ADC interface in such a way
that the sample-and-hold occurs at a specific phase of CK
user (i.e., all single conversions, and the first free running conversion) when CK
take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CK
Condition
Sample & Hold
(Cycles from Start of Convention)
Conversion Time
(Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
ADC Conversion Time
Prescaler
Reset
MUX and REFS
Update
1
2
3
Sample &
Hold
4
Conversion
5
First
14.5
25
6
7
One Conversion
8
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
9
Conversion
Single Ended
10
Conversion
Complete
Conversion,
Complete
One Conversion
Normal
11
11
1.5
13
12
ADC2
12
13
13
ATmega16/32U4
. A conversion initiated by the
ADC2
Next Conversion
1
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
ADC2
LSB of Result
2
Auto Triggered
MUX and REFS
Update
is high will take 14 ADC
Next Conversion
Convertion
equal to half the ADC
1
Prescaler
Reset
3
13.5
Sample & Hold
2
2
4
ADC2
is low will
297

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