AT89S8253-24PU Atmel, AT89S8253-24PU Datasheet

IC 8051 MCU FLASH 12K 40DIP

AT89S8253-24PU

Manufacturer Part Number
AT89S8253-24PU
Description
IC 8051 MCU FLASH 12K 40DIP
Manufacturer
Atmel
Series
89Sr
Datasheet

Specifications of AT89S8253-24PU

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Cpu Family
89S
Device Core
8051
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
SPI/UART
Total Internal Ram Size
256Byte
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Compliant

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Features
1. Description
The AT89S8253 is a low-power, high-performance CMOS 8-bit microcontroller with
12K bytes of In-System Programmable (ISP) Flash program memory and 2K bytes of
EEPROM data memory. The device is manufactured using Atmel’s high-density non-
volatile memory technology and is compatible with the industry-standard MCS-51
instruction set and pinout. The on-chip downloadable Flash allows the program mem-
ory to be reprogrammed in-system through an SPI serial interface or by a
conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with downloadable Flash on a monolithic chip, the Atmel AT89S8253 is a powerful
microcontroller which provides a highly-flexible and cost-effective solution to many
embedded control applications.
Compatible with MCS
12K Bytes of In-System Programmable (ISP) Flash Program Memory
2K Bytes EEPROM Data Memory
64-byte User Signature Array
2.7V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 24 MHz (in x1 and x2 Modes)
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Nine Interrupt Sources
Enhanced UART Serial Port with Framing Error Detection and Automatic
Address Recognition
Enhanced SPI (Double Write/Read Buffered) Serial Interface
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Programmable Watchdog Timer
Dual Data Pointer
Power-off Flag
Flexible ISP Programming (Byte and Page Modes)
Four-level Enhanced Interrupt Controller
Programmable and Fuseable x2 Clock Option
Internal Power-on Reset
42-pin PDIP Package Option for Reduced EMC Emission
Green (Pb/Halide-free) Packaging Option
– SPI Serial Interface for Program Downloading
– Endurance: 10,000 Write/Erase Cycles
– Endurance: 100,000 Write/Erase Cycles
– Page Mode: 64 Bytes/Page for Code Memory, 32 Bytes/Page for Data Memory
®
51 Products
8-bit
Microcontroller
with 12 Kbyte
Flash
AT89S8253
3286P–MICRO–3/10

Related parts for AT89S8253-24PU

AT89S8253-24PU Summary of contents

Page 1

... The on-chip downloadable Flash allows the program mem- ory to be reprogrammed in-system through an SPI serial interface conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the Atmel AT89S8253 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. ...

Page 2

... Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes ...

Page 3

... P1.0 (T2) (RD) P3 VDD XTAL2 10 33 PWRVDD XTAL1 11 32 P0.0 (AD0) GND 12 31 P0.1 (AD1) PWRGND 13 30 P0.2 (AD2) (A8) P2 P0.3 (AD3) (A9) P2 P0.4 (AD4) (A10) P2 P0.5 (AD5) (A11) P2 P0.6 (AD6) (A12) P2 P0.7 (AD7) (A13) P2 EA/VPP (A14) P2 ALE/PROG (A15) P2 PSEN AT89S8253 3 ...

Page 4

... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. AT89S8253 4 ,150 A typical) because of the weak internal pull-ups. µ ...

Page 5

... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S8253, as shown in the following table. Port Pin P3 ...

Page 6

... XTAL2 Output from the inverting oscillator amplifier. XTAL2 should not drive a board-level clock without a buffer. 4. Block Diagram PSEN ALE/PROG RST AT89S8253 6 for internal program executions. This pin also receives the 12-volt CC ) during Flash programming when 12-volt programming is PP P0 PORT 0 DRIVERS GND RAM ADDR ...

Page 7

... User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Table 5-1. AT89S8253 SFR Map and Reset Values 0F8H B 0F0H 00000000 ...

Page 8

... IP and IPH registers. IPH bits have the same functions as IP bits, except IPH has higher priority than IP. By using IPH in conjunction with IP, a priority level may be set for each interrupt. AT89S8253 8 – – ...

Page 9

... It can be set and reset under software control and is not affected by RESET. 6. Data Memory – EEPROM and RAM The AT89S8253 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. ...

Page 10

... WRTINH (Write Inhibit READ-ONLY bit which is cleared by hardware when V WRTINH of the on-chip EEPROM to be executed. When this bit is cleared, an ongoing programming cycle will be aborted or a new programming cycle will not start. Figure 6-1. Data EEPROM Write Sequence EEMEN EEMWE EELD MOVX DATA RDY/BSY AT89S8253 10 EELD EEMWE EEMEN ...

Page 11

... Memory Brown-out Protection The AT89S8253 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level of nominally 2.2V (2.4V max). The pur- pose of the BOD is to ensure that if V erased/written at voltages too low for programming. At powerup the V BOD threshold before execution starts ...

Page 12

... The WDT is disabled by Power-on Reset and during Power-down mode. When WDT times out without being serviced or disabled, an internal RST pulse is generated to reset the CPU. See Table 8-1 Table 8-1. AT89S8253 12 for the WDT period selections. Watchdog Timer Time-out Period Selection WDT Prescaler Bits ...

Page 13

... If HWDT = 1, this bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). Figure 8-1. Software Mode – Watchdog Timer Sequence WDTEN WSWRST 3286P–MICRO–3/10 PS0 WDIDLE DISRTO Writes AT89S8253 Table 8-2). Reset Value = 0000 0000B HWDT WSWRST WDTEN 0 13 ...

Page 14

... Timer 0 and 1 Timer 0 and Timer 1 in the AT89S8253 operate the same way as Timer 0 and Timer 1 in the AT89S51 and AT89S52. For more detailed information on the Timer/Counter operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 10. Timer 2 Timer 16-bit Timer/Counter that can operate as either a timer or an event counter. The ...

Page 15

... RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus- trated in 3286P–MICRO–3/10 RCLK TCLK EXEN2 Figure 10-1. AT89S8253 Reset Value = 0000 0000B TR2 C/T2 CP/RL2 Table 10-2) and T2MOD (see 15 ...

Page 16

... Setting the DCEN bit enables Timer 2 to count up or down, as shown in mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit AT89S8253 16 C/ ...

Page 17

... The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 10-2. Timer 2 in Auto Reload Mode (DCEN = 0) Figure 10-3. Timer 2 Auto Reload Mode (DCEN = 1 Timer 2 Auto Reload Mode (DCEN = 1) 3286P–MICRO–3/10 AT89S8253 17 ...

Page 18

... Normally timer, it increments every machine cycle (at 1/12 the oscillator frequency baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below. where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. AT89S8253 18 C/ TH2 TL2 ...

Page 19

... RCAP2H and RCAP2L. Figure 12-1. Timer 2 in Clock-out Mode 3286P–MICRO–3/10 Figure Oscillator Frequency Clock Out Frequency = ------------------------------------------------------------------------------------------- - × 65536 – AT89S8253 10-4. This figure is valid only if RCLK or Figure 12-1. This ( ) ] RCAP2H,RCAP2L 19 ...

Page 20

... UART The UART in the AT89S8253 operates the same way as the UART in the AT89S51 and AT89S52. For more detailed information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 13.1 Enhanced UART In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition ...

Page 21

... UART drivers which do not make use of this feature. 3286P–MICRO–3/10 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX AT89S8253 21 ...

Page 22

... Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. AT89S8253 22 – POF ...

Page 23

... Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89S8253 and peripheral devices or between multiple AT89S8253 devices. The AT89S8253 SPI features include the following: • Full-Duplex, 3-Wire Synchronous Data Transfer • Master or Slave Operation • ...

Page 24

... WCOL, and continues trans- mission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. AT89S8253 24 OSCILLATOR MSB DIVIDER ÷ ...

Page 25

... Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE. 2. Enable the master SPI prior to the slave device. 3. Slave echoes master on next Tx if not loaded with new data. 3286P–MICRO–3/10 DORD MSTR CPOL AT89S8253 Reset Value = 0000 0100B CPHA SPR1 SPR0 follows: OSC. ...

Page 26

... When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. Table 14-3. SPDR – SPI Data Register SPDR Address = 86H Not Bit Addressable SPD7 SPD6 Bit 7 6 AT89S8253 26 LDEN – – SPD5 SPD4 SPD3 ...

Page 27

... Oscillator Period Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time Serial Output Hold Time Serial Output Valid Time AT89S8253 Serial Slave 2 MUX Serial Out LATCH CLK Parallel Slave ...

Page 28

... SOX t SSE t SSD Figure 14-4. SPI Master Timing (CPHA = 0) (CPOL = 0) (CPOL = 1) MISO MOSI AT89S8253 28 SPI Slave Characteristics Parameter Oscillator Period Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time ...

Page 29

... Figure 14-6. SPI Master Timing (CPHA = 1) (CPOL = 0) (CPOL = 1) Figure 14-7. SPI Slave Timing (CPHA = 1) (CPOL = 0) (CPOL = 1) 3286P–MICRO–3/ SCK SSE t SHSL SCK SCK t SLSH t SOE SS SCK SCK MISO MOSI SS SCK SCK MISO MOSI AT89S8253 SLSH t SHSL t t SOV SOH t SIS SOV t SSD t SOX t SIH 29 ...

Page 30

... Note: *Not defined but normally LSB of previously transmitted character 15. Interrupts The AT89S8253 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE ...

Page 31

... External Interrupt 0 Priority Low 3286P–MICRO–3/10 Source RST or POR IE0 TF0 IE1 TF1 SPIF ET2 ES ET1 PT2 PS PT1 AT89S8253 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H Reset Value = 0X00 0000B EX1 ET0 EX0 Reset Value = XX00 0000B PX1 PT0 PX0 2 1 ...

Page 32

... PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External Interrupt 1 Priority High PT0H Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High Figure 15-1. Interrupt Sources AT89S8253 32 PT2H PSH PT1H Reset Value = XX00 0000B PX1H PT0H PX0H ...

Page 33

... C1 ~10 pF (A) Low Frequency C1 0–10 pF for Crystals = 0–10 pF for Ceramic Resonators R1 = 4–5 MΩ Quartz Crystal Clock Input Frequency (MHz) AT89S8253 Figure 16-1 (A) and (B). Either a quartz Figure 16-2, 16-3, 16-4 and C2 R1 (B) High Frequency C1=C2=0pF C1=C2=5pF C1=C2=10pF 16-5 illustrate ~10 pF ...

Page 34

... Figure 16-3. Quartz Crystal Clock Source (B) Figure 16-4. Ceramic Resonator Clock Source (A) AT89S8253 34 Quartz Crystal Clock Input Frequency (MHz) Ceramic Resonator Clock Input Frequency (MHz) C2=0pF C2=5pF C2=10pF R1=4MΩ C1=C2=0pF C1=C2=5pF C1=C2=10pF 3286P–MICRO–3/10 ...

Page 35

... Ceramic Resonator Clock Input Frequency (MHz) Figure 16-6. AT89S8253 C2=0pF C2=5pF C2=10pF R1=4MΩ ...

Page 36

... Exit from power-down mode. 19. Program Memory Lock Bits The AT89S8253 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated ...

Page 37

... The code and data memory arrays in the AT89S8253 are programmed byte-by-byte or by page in either programming mode. To reprogram any non-blank byte in the parallel or serial mode, the user needs to invoke the Chip Erase operation first to erase both arrays since there is no built-in auto-erase capability ...

Page 38

... Set RST and EA pins to “L”. e. Turn V Data Polling: The AT89S8253 features DATA Polling to indicate the end of any programming cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the last loaded byte will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode) ...

Page 39

... XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 24 MHz oscillator clock, the maximum SCK frequency is 1.5 MHz. 23. Serial Programming Algorithm To program and verify the AT89S8253 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. ...

Page 40

... For Page Read/Write, the data always starts from byte 63. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all bytes are shifted in/out. Then the next instruction will be ready to be decoded. AT89S8253 40 Instruction Format ...

Page 41

... ALE RST PSEN EA P3 1.0 µs 12V H L 1.0 µs 12V 12V H L 1.0 µs 12V 12V H L 1.0 µs 12V 12V H L 1.0 µs 12V 12V 12V H L 1.0 µs 12V 12V AT89S8253 Data I/O P3.4 P3.5 P3.6 P3.7 P0.7 ...

Page 42

... P1 CC 0000H/37FFH P2 A13 P3.3 ALE P3.4 P3.5 P3.6 P3.7 EA P3.0 3-24 MHz XTAL1 RST EXTERNAL CLOCK GND PSEN Oscillator Bypass Fuse (Fuse4) On AT89S8253 ADDR 0000H/37FFH P0 P2 A13 P3.3 ALE P3.4 P3.5 P3.6 P3.7 EA 3-24 MHz XTAL1 RST EXTERNAL CLOCK GND ...

Page 43

... XTAL2 3-24 MHz XTAL1 GND Oscillator Bypass Fuse (Fuse4) Off 3286P–MICRO–3/10 2. INSTRUCTION INPUT DATA OUTPUT CLOCK IN 3-24 MHz RST V EXTERNAL IH CLOCK AT89S8253 2.7V to 5.5V AT89S8253 V CC P1.5/MOSI P1.6/MISO P1.7/SCK XTAL1 RST V IH GND Oscillator Bypass Fuse (Fuse4 ...

Page 44

... Address to Data Verify Valid VFY t PROG Setup to V PSTP t PROG Hold after V PHLD t PROG Low to XTAL Halt PLX t XTAL Halt to RST Low XRL t RST Low to Power Off PWRDN Notes: 1. Power On occurs once Chip Erase. AT89S8253 44 (1) High PP Low PP reaches 2.4V. Min Max 11.5 12.5 1 ...

Page 45

... Figure 26-1. Flash/EEPROM Programming and Verification Waveforms – Parallel Mode 3286P–MICRO–3/10 AT89S8253 45 ...

Page 46

... SCK Pulse Width Low SLSH t MOSI Setup to SCK Low OVSL t MOSI Hold after SCK Low SHOX t SCK High to MISO Valid SHIV t Chip Erase Instruction Cycle Time ERASE t Serial Page Write Cycle Time SWC AT89S8253 MSB MSB Change Sample Outputs Inputs t OVSL t SHOX = -40° 85° ...

Page 47

... OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89S8253 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...

Page 48

... Data Valid to WR High QVWH t Data Hold after WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH t Address Hold after High WHAX AT89S8253 48 = -40°C to 85°C and V = 2.7 to 5.5V, unless otherwise noted Variable Oscillator Min Max Units 0 24 MHz 2t ...

Page 49

... External Program Memory Read Cycle 33. External Data Memory Read Cycle 3286P–MICRO–3/10 AT89S8253 49 ...

Page 50

... External Data Memory Write Cycle 35. External Clock Drive Waveforms 36. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89S8253 2.7V to 5.5V CC Min Max Units MHz 3286P–MICRO–3/10 ...

Page 51

... AC Testing Input/Output Waveforms Note Inputs during testing are driven at V min. for a logic 1 and V IL (1) 40. Float Waveforms 3286P–MICRO–3/10 (1) - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made max. for a logic 0. AT89S8253 Variable Oscillator Min Max Units IH 51 ...

Page 52

... CC 42. I Test Condition, Idle Mode, All Other Pins are Disconnected CC 43. Clock Signal Waveform for CLCH CHCL V - 0.5V CC 0.45V 44. I Test Condition, Power-down Mode, All Other Pins are Disconnected 5.5V CC AT89S8253 RST P0 EA (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS RST (NC) XTAL2 CLOCK SIGNAL ...

Page 53

... I (Active Mode) Measurements CC AT89S8253 I CC With Internal Clock Oscillator x1 Mode 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz) AT89S8253 I CC With Internal Clock Oscillator x1 Mode 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz) AT89S8253 o Active @ Active @ 3.0V 4.0V 5.0V 3.0V 4.0V 5.0V ...

Page 54

... I (Idle Mode) Measurements CC 47. I (Power Down Mode) Measurements CC AT89S8253 54 AT89S8253 I Idle vs. Frequency 25°C CC With Internal Clock Oscillator x1 Mode 3 2.5 2 1 Frequency (MHz) AT89S8253 I in Power-down CC 2.5 2 1 deg C 25 deg C 90 deg ...

Page 55

... Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 42PS6 42-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 3286P–MICRO–3/10 Ordering Code AT89S8253-24AU AT89S8253-24JU AT89S8253-24PU AT89S8253-24PSU Package Type AT89S8253 Package Operation Range 44A 44J Industrial (-40 ° ...

Page 56

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S8253 TITLE 44A, 44-lead Body Size, 1 ...

Page 57

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3286P–MICRO–3/10 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89S8253 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...

Page 58

... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89S8253 58 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...

Page 59

... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3286P–MICRO–3/10 D PIN TITLE 42PS6, 42-lead (Shrink 0.070"/0.600” Row Space) Plastic Dual Inline Package (PDIP) AT89S8253 E1 A1 COMMON DIMENSIONS (Unit of Measure = Inch) MIN SYMBOL NOM A – – A1 0.020 – D 1.440 1 ...

Page 60

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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