ATMEGA16-16AQ Atmel, ATMEGA16-16AQ Datasheet

MCU AVR 16K FLASH 16MHZ 44-TQFP

ATMEGA16-16AQ

Manufacturer Part Number
ATMEGA16-16AQ
Description
MCU AVR 16K FLASH 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA16-16AQ

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– 2.7V - 5.5V for ATmega16L
– 4.5V - 5.5V for ATmega16
– 0 - 8 MHz for ATmega16L
– 0 - 16 MHz for ATmega16
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 µA
True Read-While-Write Operation
Mode
and Extended Standby
In-System Programming by On-chip Boot Program
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega16
ATmega16L
Rev. 2466T–AVR–07/10

Related parts for ATMEGA16-16AQ

ATMEGA16-16AQ Summary of contents

Page 1

... ATmega16L – 4.5V - 5.5V for ATmega16 • Speed Grades – MHz for ATmega16L – MHz for ATmega16 • Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA ® ® AVR ...

Page 2

... Pin Figure 1. Pinout ATmega16 Configurations Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2466T–AVR–07/10 PDIP (XCK/T0) PB0 (T1) PB1 ...

Page 3

... Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. Block Diagram Figure 2 ...

Page 4

... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effec- tive solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16 as listed on 58. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 2466T–AVR–07/10 1. ATmega16(L) 6 ...

Page 7

... These code examples assume that the part specific header file is included before Examples compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documen- tation for more details. 2466T–AVR–07/10 ATmega16(L) 7 ...

Page 8

... Program Flash Counter and Control Program Memory Instruction General Purpose Register Registrers Instruction Decoder Control Lines SRAM EEPROM I/O Lines ATmega16(L) Data Bus 8-bit Status Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data I/O Module 2 I/O Module n ...

Page 9

... The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. 2466T–AVR–07/ R/W R/W R/W R/W R ATmega16( SREG R/W R/W R ...

Page 10

... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2466T–AVR–07/10 ⊕ V ATmega16(L) 10 ...

Page 11

... R13 General R14 Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4, each register is also assigned a data memory address, mapping them ATmega16(L) 0 Addr. $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register Low Byte $1B X-register High Byte $1C Y-register Low Byte $1D ...

Page 12

... YH 7 R29 ($1D R31 ($1F SP15 SP14 SP13 SP12 SP11 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R ATmega16(L) Figure R26 ($1A R28 ($1C R30 ($1E SP10 SP9 SP8 SPH SP3 SP2 SP1 SP0 SPL R/W R/W R/W R/W R/W R/W R/W R/W 0 ...

Page 13

... Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU clk CPU Total Execution Time Result Write Back for details. ATmega16( “Interrupts” on page T4 T4 “Memory Program- 45 ...

Page 14

... EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2466T–AVR–07/10 “Boot Loader Support – Read-While-Write Self- 246. ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ ATmega16(L) “Interrupts” on page 45 for more 14 ...

Page 15

... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2466T–AVR–07/10 ; set global interrupt enable ATmega16(L) 15 ...

Page 16

... Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16 Pro- gram Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in 246 ...

Page 17

... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega16 are all accessible through all these addressing modes. The Register File is described in Figure 9. Data Memory Map 2466T– ...

Page 18

... SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega16 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles ...

Page 19

... Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...

Page 20

... The examples 2466T–AVR–07/10 Number of Calibrated RC Symbol Oscillator Cycles 1. Uses 1 MHz clock, independent of CKSEL Fuse setting. ATmega16(L) for details about boot Table 1 lists the typical pro- (1) Typ Programming Time 8448 8.5 ms “ ...

Page 21

... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega16(L) 21 ...

Page 22

... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, ATmega16(L) 22 ...

Page 23

... I/O Memory The I/O space definition of the ATmega16 is shown in All ATmega16 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working regis- ters and the I/O space. I/O Registers within the address range $00 - $1F are directly bit- accessible using the SBI and CBI instructions ...

Page 24

... I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC External Clock Oscillator Oscillator is halted, enabling TWI address reception in all sleep modes. I/O ATmega16(L) Figure CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog ...

Page 25

... For all fuses “1” means unprogrammed while “0” means programmed. 299. = 5.0V) Typ Time-out ( ATmega16(L) CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 = 3.0V) Number of Cycles CC 4 (4,096 64K (65,536) Figure 12. Either a quartz crystal or a Table “ATmega16 Typ- 25 ...

Page 26

... This option should not be used with crystals, only with ceramic resonators. ATmega16(L) Table 4. For ceramic resonators, the XTAL2 XTAL1 GND Table 4. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...

Page 27

... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATmega16(L) Additional Delay from Reset ( ...

Page 28

... These options should only be used if frequency stability at start-up is not important for the application CKSEL3..0 0101 0110 0111 1000 ATmega16(L) = 5.0V) Recommended Usage Fast rising power or BOD enabled Slowly rising power Stable frequency at start-up Reserved NC XTAL2 XTAL1 GND Frequency Range (MHz) 0.1 ≤ 0.9 ...

Page 29

... The device is shipped with this option selected. Start-up Time from Additional Delay Power-down and Power-save The device is shipped with this option selected. ATmega16(L) = 5.0V) Recommended Usage – BOD enabled Fast rising power Slowly rising power Fast rising power or BOD enabled Table 9 ...

Page 30

... CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value Table 11. Min Frequency in Percentage of Nominal Frequency (%) $00 50 $7F 75 100 ATmega16( CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 OSCCAL 30 ...

Page 31

... Start-up Time from Additional Delay Power-down and Power-save The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF. ATmega16(L) from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4.1 ms Fast rising power ...

Page 32

... To avoid the MCU entering the sleep mode unless it is the programmers purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 2466T–AVR–07/10 presents the different clock systems in the ATmega16, and their distribu ...

Page 33

... Timer/Counter2 if clocked asynchronously. 2466T–AVR–07/10 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page , allowing operation only of asynchronous ASY ATmega16(L) , and clk , while allowing the CPU FLASH “External Interrupts” on page 68 25. 33 ...

Page 34

... External Crystal or resonator selected as clock source bit in ASSR is set. 3. Only INT2 or level interrupt INT1 and INT0. 2466T–AVR–07/10 Oscillators Main Clock Timer Osc. clk Source Enabled Enabled ADC ASY ( ( ATmega16(L) Wake-up Sources INT2 TWI INT1 Address Timer EEPROM INT0 Match 2 ( ( (2) (3) ( (3) ...

Page 35

... ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 54 /2, the input buffer will use excessive power. CC ATmega16(L) “Analog to Digital Converter” on page 204 for details on how to for details on how to “Internal Volt- ) are stopped, the input buffers of the ...

Page 36

... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 2466T–AVR–07/10 ATmega16(L) 36 ...

Page 37

... CKSEL Fuses. The different selec- tions for the delay period are presented in Reset Sources The ATmega16 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...

Page 38

... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega16L and BODLEVEL = 0 for ATmega16. BODLEVEL = 1 is not applicable for ATmega16. ATmega16(L) DATA BUS ...

Page 39

... Table 15. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT TIME-OUT INTERNAL RESET V POT V CC RESET TIME-OUT INTERNAL RESET ATmega16(L) is below the detection level. The RST t TOUT 39 ...

Page 40

... Time-out period t Figure 18. External Reset During Operation Brown-out Detection ATmega16 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...

Page 41

... Reset Flags. 2466T–AVR–07/10 for details on operation of the Watchdog Timer JTD ISC2 – JTRF R/W R ATmega16( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description . Refer to TOUT 41 ...

Page 42

... Internal Voltage ATmega16 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference The voltage reference has a start-up time that may influence the way it should be used. The ...

Page 43

... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

Page 44

... WDTCR ori r16, (1<<WDTOE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega16(L) 44 ...

Page 45

... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega16. For a general explanation of the AVR interrupt handling, refer to page 13. Interrupt Vectors in ATmega16 Table 18. Reset and Interrupt Vectors Vector No Notes: Table 19 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...

Page 46

... Table 19. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16 is: Address $000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 ...

Page 47

... RESET: ldi r16,high(RAMEND) ; Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ATmega16(L) Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...

Page 48

... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 246 ATmega16( – ...

Page 49

... Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret /* Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); ATmega16(L) 49 ...

Page 50

... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O Ports” on page 55. Refer to the individual module sections for a full description of the alter- ATmega16(L) Figure 22. Refer to “Electrical Charac Logic See Figure 23 "General Digital I/O" for Details 66 ...

Page 51

... SLEEP CONTROL clk : I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 66, the DDxn bits are accessed at the DDRx I/O address, the ATmega16( DDxn Q CLR RESET Q ...

Page 52

... Output Figure 23, the PINxn Register bit and the preceding latch consti- and t pd,max SYSTEM CLK XXX SYNC LATCH PINxn r17 and t pd,max pd,min ATmega16(L) Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No ...

Page 53

... INSTRUCTIONS SYNC LATCH 2466T–AVR–07/10 Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the through the synchronizer is one system clock period. pd r16 out PORTx, r16 PINxn r17 ATmega16(L) 0xFF nop in r17, PINx 0x00 t pd 0xFF 53 ...

Page 54

... Figure 23, the digital input signal can be clamped to ground at the input of the /2. CC ATmega16(L) “Alternate Port Functions” on page 55. 54 ...

Page 55

... DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. All other signals are unique for each pin. ATmega16(L) Figure 23 can be overridden by alter- PUOExn PUOVxn ...

Page 56

... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog Input/ output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. ATmega16(L) Fig- 56 ...

Page 57

... ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) and Table 24 relate the alternate functions of Port A to the overriding signals shown in 55. PA7/ADC7 PA6/ADC6 – ADC7 INPUT ADC6 INPUT ATmega16( ACME PUD PSR2 PSR10 R/W R/W R/W R Table PA5/ADC5 PA4/ADC4 ...

Page 58

... MOSI (SPI Bus Master Output/Slave Input) SS (SPI Slave Select Input) AIN1 (Analog Comparator Negative Input) OC0 (Timer/Counter0 Output Compare Match Output) AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) T1 (Timer/Counter1 External Counter Input) T0 (Timer/Counter0 External Counter Input) XCK (USART External Clock Input/Output) ATmega16(L) PA1/ADC1 PA0/ADC0 ...

Page 59

... Figure 26 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 2466T–AVR–07/10 and Table 27 relate the alternate functions of Port B to the overriding signals shown in 55. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, ATmega16(L) 59 ...

Page 60

... OC0 ENABLE 0 OC0 0 0 INT2 ENABLE 0 1 – INT2 INPUT AIN1 INPUT AIN0 INPUT ATmega16(L) PB5/MOSI PB4/SS SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR 0 SPI MSTR OUTPUT ...

Page 61

... TOSC1 (Timer Oscillator Pin 1) TDI (JTAG Test Data In) TDO (JTAG Test Data Out) TMS (JTAG Test Mode Select) TCK (JTAG Test Clock) SDA (Two-wire Serial Bus Data Input/Output Line) SCL (Two-wire Serial Bus Clock Line) ATmega16(L) Table 28. If the JTAG interface is enabled, 61 ...

Page 62

... Port C to the overriding signals shown in 55. PC7/TOSC2 PC6/TOSC1 AS2 AS2 0 0 AS2 AS2 AS2 AS2 0 0 – – T/C2 OSC OUTPUT T/C2 OSC INPUT ATmega16(L) PC5/TDI PC4/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI – 62 ...

Page 63

... ICP1 (Timer/Counter1 Input Capture Pin) OC1A (Timer/Counter1 Output Compare A Match Output) OC1B (Timer/Counter1 Output Compare B Match Output) INT1 (External Interrupt 1 Input) INT0 (External Interrupt 0 Input) TXD (USART Output Pin) RXD (USART Input Pin) ATmega16(L) (1) PC1/SDA PC0/SCL TWEN TWEN PORTC1 • PUD PORTC0 • ...

Page 64

... DIEOV DI AIO 2466T–AVR–07/10 and Table 33 relate the alternate functions of Port D to the overriding signals shown in 55. PD7/OC2 PD6/ICP1 OC2 ENABLE 0 OC2 – ICP1 INPUT – – ATmega16(L) PD5/OC1A PD4/OC1B OC1A ENABLE OC1B ENABLE OC1A OC1B – – – – 64 ...

Page 65

... PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2466T–AVR–07/10 PD3/INT1 PD2/INT0 INT1 ENABLE INT0 ENABLE 1 1 INT1 INPUT INT0 INPUT – – ATmega16(L) PD1/TXD PD0/RXD TXEN RXEN 0 PORTD0 • PUD TXEN RXEN 1 0 TXEN 0 TXD – RXD – – 65 ...

Page 66

... PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R PINB7 PINB6 PINB5 PINB4 N/A N/A N/A N/A ATmega16( PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R PINA3 PINA2 PINA1 PINA0 ...

Page 67

... PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega16( PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...

Page 68

... The low level of INT1 generates an interrupt request. 1 Any logical change on INT1 generates an interrupt request. 0 The falling edge of INT1 generates an interrupt request. 1 The rising edge of INT1 generates an interrupt request. ATmega16(L) 24. Low level interrupts on INT0/INT1 and the 291. The MCU will “System Clock and ...

Page 69

... Table 36 will generate an interrupt. Shorter pulses are not guaranteed to Parameter Minimum pulse width for asynchronous external interrupt INT1 INT0 INT2 – R/W R/W R ATmega16( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description Condition Min Typ Max – ...

Page 70

... INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See Modes” on page 54 2466T–AVR–07/ INTF1 INTF0 INTF2 – R/W R/W R for more information. ATmega16( – – – – GIFR “Digital Input Enable and Sleep 70 ...

Page 71

... The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). 2466T–AVR–07/10 “Pinout ATmega16” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...

Page 72

... Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clk Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source ATmega16(L) 87. TOVn (Int. Req.) Clock Select Edge Detector clk ...

Page 73

... A CPU write overrides (has priority over) all counter clear or T0 76. (See “Modes of Operation” on page shows a block diagram of the output compare unit. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega16(L) 76.). TCNTn OCFn (Int.Req.) OCn COMn1:0 73 ...

Page 74

... COM01:0 bits are shown. When referring to the OC0 state, the reference is for the internal OC0 Register, not the OC0 pin System Reset occur, the OC0 Register is reset to “0”. 2466T–AVR–07/10 ATmega16(L) Figure 30 shows a simplified schematic of 74 ...

Page 75

... For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. 2466T–AVR–07/10 COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 83. Table 39 on page 84. For fast PWM mode, refer to Table 41 on page ATmega16( OCn PORT D Q DDR Table 40 on page 84. ...

Page 76

... CTC mode does not have 2466T–AVR–07/10 74.). Figure 34, Figure 81. 0 Flag in this case behaves like a ninth TOV 0 Flag, the timer resolution can be increased by software. TOV Figure ATmega16(L) 35, Figure 36 and Figure will be set in the same TOV 31. The counter value (TCNT0) OCn Interrupt Flag Set (COMn1 ...

Page 77

... OCn Figure 32. The TCNT0 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period ATmega16(L) f clk_I/O ---------------------------------------------- - ⋅ ⋅ OCRn 1 + OCRn Interrupt Flag Set OCRn Update and ...

Page 78

... MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.) 2466T–AVR–07/10 ATmega16(L) Table 40 on page 84). The actual OC0 value will ...

Page 79

... OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The 2466T–AVR–07/ Table 41 on page ATmega16(L) Figure 33. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 84) ...

Page 80

... The Timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 2466T–AVR–07/10 f clk_I ----------------- - OCnPCPWM ⋅ N 510 Figure 33 OCn has a transition from high to low even though there Figure 33. When the OCR0A value is MAX the ATmega16(L) 80 ...

Page 81

... Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. ATmega16( therefore shown MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 81 ...

Page 82

... TCNTn (CTC) OCRn OCFn 2466T–AVR–07/10 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. /8) I/O Tn /8) I/O TOP - 1 ATmega16(L) OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 82 ...

Page 83

... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega16( WGM01 CS02 CS01 CS00 R/W ...

Page 84

... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See 79 for more details. ATmega16(L) (1) “Fast PWM Mode” on page 77 (1) “Phase Correct PWM Mode” on page ...

Page 85

... External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R ATmega16( R/W R/W R/W R R/W R/W R/W R OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R TCNT0 OCR0 TIMSK 85 ...

Page 86

... Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. 2466T–AVR–07/ OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R/W R ATmega16( TOV1 OCF0 TOV0 TIFR R/W R/W R ...

Page 87

... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATmega16(L) /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 38 ). The latch ...

Page 88

... This bit will always be read as zero. 2466T–AVR–07/10 I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ADTS2 ADTS1 ADTS0 R/W R/W R ATmega16(L) (1) T1 T1/T0) is shown in Figure – ACME PUD PSR2 PSR10 R R/W R/W R/W ...

Page 89

... I/O pins, are shown in bold. The device specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 2466T–AVR–07/10 Figure 1 on page 2. CPU accessible I/O Registers, including I/O 110. ATmega16(L) Figure 40. For the actual 89 ...

Page 90

... Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1 on page 2, Timer/Counter1 pin placement and description. The compare match event will also set the Compare Match ATmega16(L) (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int ...

Page 91

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Regis- ter. The assignment is dependent of the mode of operation. ATmega16(L) (See 91 ...

Page 92

... Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See “About Code Examples” on page 7. ATmega16(L) 92 ...

Page 93

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 7. ATmega16(L) 93 ...

Page 94

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page 7. “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega16(L) 87. 94 ...

Page 95

... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega16(L) TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 101 ...

Page 96

... Low byte is written to ICR1L. 2466T–AVR–07/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ATmega16(L) Figure 42. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) ...

Page 97

... Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 2466T–AVR–07/10 92. ATmega16(L) “Accessing 16-bit Registers” (Figure 38 on page 87). The edge detector is also 97 ...

Page 98

... The small “n” in the register and bit DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega16(L) 101.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...

Page 99

... Normal mode. The OC1x Register keeps its value even when changing between waveform generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 2466T–AVR–07/10 92. ATmega16(L) “Accessing 16-bit Registers” 99 ...

Page 100

... For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 2466T–AVR–07/10 COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O See “16-bit Timer/Counter Register Description” on page 110. Table 44 on page ATmega16(L) Figure 44 shows a simplified Q 1 OCnx OCnx Pin DDR Table 44, Table 45 and Table 46 110 ...

Page 101

... OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 2466T–AVR–07/10 100.) “Timer/Counter Timing Diagrams” on page Figure ATmega16(L) 108. 45. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 101 ...

Page 102

... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 2466T–AVR–07/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ FPWM ATmega16(L) f clk_I/O ⋅ OCRnA TOP log 1 + ---------------------------------- - log Figure 46 ...

Page 103

... OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). 2466T–AVR–07/ ATmega16(L) OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set OCnA Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

Page 104

... TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter- rupt Flag will be set when a compare match occurs. 2466T–AVR–07/10 f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I TOP log + ---------------------------------- - PCPWM log ATmega16(L) ) Figure 47. The figure 104 ...

Page 105

... OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when 2466T–AVR–07/ ATmega16(L) OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set ...

Page 106

... PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 2466T–AVR–07/10 f OCnxPCPWM 48). R PFCPWM Figure 48. The figure shows phase and frequency correct PWM ATmega16(L) f clk_I/O = --------------------------- - ⋅ ⋅ TOP ( ) TOP ...

Page 107

... PWM mode. If the OCR1x is set equal to BOTTOM the 2466T–AVR–07/ shows the output generated is, in contrast to the phase correct mode, symmetrical f OCnxPFCPWM ATmega16(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) ...

Page 108

... I/O Tn /8) I/O OCRnx - 1 shows the count sequence close to TOP in various modes. When using phase and ATmega16( therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value OCRnx ...

Page 109

... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega16(L) TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 ...

Page 110

... COM1B1 COM1B0 R/W R/W R/W R Table 44 COM1A0/COM1B0 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM ATmega16( FOC1A FOC1B WGM11 WGM10 W W R/W R shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected. ...

Page 111

... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 104. ATmega16(L) (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OCnA/OCnB disconnected ...

Page 112

... PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ATmega16(L) (See “Modes of Operation” on page Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF ...

Page 113

... I clk /64 (From prescaler) I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. ATmega16( WGM12 CS12 CS11 CS10 TCCR1B R/W R/W R/W R Figure 113 ...

Page 114

... OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R/W R See “Accessing 16-bit Registers” on page 92 ICR1[15:8] ICR1[7:0] R/W R/W R/W R/W R ATmega16( TCNT1H TCNT1L R/W R/W R See “Accessing 16-bit OCR1AH OCR1AL R/W R/W R OCR1BH OCR1BL R/W R/W R ...

Page 115

... OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega16( OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R/W ...

Page 116

... TOV1 Flag is set when the timer overflows. Refer to behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 2466T–AVR–07/10 ATmega16(L) Table 47 on page 112 for the TOV1 Flag 116 ...

Page 117

... Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- tive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 2466T–AVR–07/10 “Pinout ATmega16” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...

Page 118

... Increment or decrement TCNT2 by 1. Selects between increment and decrement. Clear TCNT2 (set all bits to zero). Timer/Counter clock. Signalizes that TCNT2 has reached maximum value. ATmega16(L) See “Output Compare Table 49 are also used extensively 131. For details on clock sources and prescaler, see TOVn (Int ...

Page 119

... A CPU write overrides (has priority over) all counter clear or T2 122. can be used for generating a CPU interrupt. TOV2 122). Figure 55 shows a block diagram of the output compare unit. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega16(L) (“Modes of Operation” TCNTn OCFn (Int.Req.) OCxy COMn1:0 119 ...

Page 120

... Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. 2466T–AVR–07/10 ATmega16(L) 120 ...

Page 121

... FOC2 strobe bits. 2466T–AVR–07/10 COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 128. Table 51 on page 129. For fast PWM mode, refer to Table 53 on page ATmega16(L) Figure 56 shows a simplified schematic OCn Pin OCn PORT ...

Page 122

... Timing Diagrams” on page TOV2 Flag, the timer resolution can be increased by software. There TOV2 Figure ATmega16(L) 126. ) will be set in the same TOV2 Flag in this case behaves like a ninth 57. The counter value (TCNT2) OCn Interrupt Flag Set (COMn1 122 ...

Page 123

... OCn Figure 58. The TCNT2 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period set each time the counter reaches MAX. If the inter- TOV2 ATmega16(L) f clk_I/O ---------------------------------------------- - ⋅ ⋅ OCRn 1 + Flag is set in the same timer clock cycle that the TOV2 ...

Page 124

... The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. 2466T–AVR–07/10 ATmega16(L) Table 52 on page 129). The actual OC2 value f ...

Page 125

... Compare Match and hence the OCn that would have happened on the way up. 2466T–AVR–07/10 TCNTn OCn OCn Period 1 TOV2 f OCnPCPWM Figure 59 ATmega16(L) OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 set each time the counter reaches BOTTOM. The Table 53 on page 129). The actual OC2 ...

Page 126

... Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. ATmega16(L) should be replaced by I/O MAX BOTTOM /8) clk_I/O MAX BOTTOM ) T2 BOTTOM + 1 BOTTOM + 1 ...

Page 127

... TCNTn (CTC) OCRn OCFn 2466T–AVR–07/10 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. /8) I/O Tn /8) I/O TOP - 1 ATmega16(L) OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 127 ...

Page 128

... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega16( WGM21 CS22 CS21 CS20 R/W ...

Page 129

... A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See 124 for more details. ATmega16(L) (1) “Fast PWM Mode” on page 123 (1) “Phase Correct PWM Mode” on page ...

Page 130

... T2S clk 0 0 /64 (From prescaler) T2S clk 0 1 /128 (From prescaler) T2S 1 0 clk /256 (From prescaler clk /1024 (From prescaler TCNT2[7:0] R/W R/W R/W R OCR2[7:0] R/W R/W R/W R ATmega16( TCNT2 R/W R/W R/W R OCR2 R/W R/W R/W R Table 130 ...

Page 131

... Write new values to TCNT2, OCR2, and TCCR2 switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. 2466T–AVR–07/ – – – – AS2 R ATmega16( TCN2UB OCR2UB TCR2UB ASSR When AS2 is I/O 131 ...

Page 132

... TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 2466T–AVR–07/10 ATmega16(L) ) again becomes active, TCNT2 will read as the previous I/O 132 ...

Page 133

... PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. 2466T–AVR–07/ OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R ATmega16( TOIE1 OCIE0 TOIE0 TIMSK R/W R/W R/W R TOV1 OCF0 TOV0 TIFR R/W R/W R/W R 133 ...

Page 134

... Additionally, clk T2S T2S ADTS2 ADTS1 ADTS0 – R/W R/W R ATmega16(L) 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S /8, clk T2S T2S as well as 0 (stop) may be selected. T2S ACME PUD ...

Page 135

... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16 and peripheral devices or between several AVR devices. The ATmega16 SPI Peripheral includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...

Page 136

... SPI SCK CLOCK GENERATOR SS Table 55 on page 136. For more details on automatic port overrides, refer to 55. Direction, Master SPI User Defined Input User Defined User Defined ATmega16(L) MSB SLAVE LSB MISO 8 BIT SHIFT REGISTER MOSI SHIFT SCK ENABLE SS Direction, Slave SPI ...

Page 137

... For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 2466T–AVR–07/10 See “Alternate Functions of Port B” on page 58 direction of the user defined SPI pins. ATmega16(L) for a detailed description of how to define the 137 ...

Page 138

... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 7. ATmega16(L) 138 ...

Page 139

... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page 7. ATmega16(L) 139 ...

Page 140

... When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. 2466T–AVR–07/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R ATmega16( CPHA SPR1 SPR0 SPCR R/W R/W R 140 ...

Page 141

... Figure 68 Leading Edge 0 Rising 1 Falling Figure 67 Leading Edge 0 Sample 1 Setup SPR1 SPR0 ATmega16(L) for an example. The CPOL functionality is summa- Trailing Edge Falling Rising and Figure 68 for an example. The CPHA func- Trailing Edge Setup Sample SCK Frequency osc osc osc 128 ...

Page 142

... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega16 is also used for program memory and EEPROM download- ing or uploading. See SPI Data Register – SPDR ...

Page 143

... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega16(L) Trailing Edge SPI Mode Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 ...

Page 144

... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1 on page 2, Table 33 on page placement. ATmega16(L) Figure 69. CPU accessible I/O Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN ...

Page 145

... The XCK pin is only active when using Synchronous mode. Figure 70 2466T–AVR–07/10 shows a block diagram of the clock generation logic. ATmega16(L) Figure 69) if the Buffer Registers are 145 ...

Page 146

... Input from XCK pin (Internal Signal). Used for synchronous Slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous Master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculating ATmega16(L) U2X / ...

Page 147

... BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps). System Oscillator clock frequency Figure 70 for details. depends on the stability of the system clock source therefore recommended to osc ATmega16(L) Equation for Calculating UBRR (1) Baud Rate Value f OSC UBRR ...

Page 148

... UCPOL is zero the data will be changed at ris- illustrates the possible combinations of the frame formats. Bits inside brackets are (IDLE Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. ATmega16(L) Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 148 ...

Page 149

... No transfers on the communication line (RxD or TxD). An IDLE line must be high. ⊕ … even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity Data bit n of the character ATmega16(L) ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ d ...

Page 150

... Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); 1. See “About Code Examples” on page 7. ATmega16(L) 150 ...

Page 151

... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page 7. ATmega16(L) 151 ...

Page 152

... UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRB is static. (that is, only the TXB8 bit of the UCSRB Register is used after initialization). ATmega16(L) 152 ...

Page 153

... The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing Transmitter and pending transmissions are completed, that is, when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no lon- ger override the TxD pin. 2466T–AVR–07/10 ATmega16(L) 153 ...

Page 154

... UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret (1) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page 7. ATmega16(L) 154 ...

Page 155

... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 7. ATmega16(L) 155 ...

Page 156

... The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. 2466T–AVR–07/10 and “Parity Checker” on page 156. ATmega16(L) 156 ...

Page 157

... Double Speed mode (indicated with sample numbers inside boxes on the 2466T–AVR–07/10 (1) sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; 1. See “About Code Examples” on page 7. IDLE ATmega16(L) START Figure 73 BIT 157 ...

Page 158

... Figure shows the sampling of the stop bit and the earliest possible beginning of the start bit Figure 75. For Double Speed mode the first low level must be delayed to (B). ATmega16(L) shows the sampling of the data bits and the parity BIT STOP 1 (A) ( ...

Page 159

... D R (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104.35 ATmega16( ------------------------------------------ - D S ⋅ – ----------------------------------- ( ) for Normal Speed and for Normal Speed and M Max Total Recommended Max Error (%) Receiver Error (%) +6 ...

Page 160

... In this case an UBRR value that gives an acceptable low error can be used if possible. 2466T–AVR–07/ (%) R (%) slow fast 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega16(L) Max Total Recommended Max Error (%) Receiver Error (%) +3.90/-4.00 ±1.5 +3.53/-3.61 ±1.5 +3.23/-3.30 ±1.0 160 ...

Page 161

... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. 2466T–AVR–07/10 ATmega16(L) 161 ...

Page 162

... UCSRC,r16 ... (1) ... /* Set UBRRH UBRRH = 0x02; ... /* Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... 1. See “About Code Examples” on page 7. ATmega16(L) 162 ...

Page 163

... SBIS), since these also will change the state of the FIFO. 2466T–AVR–07/10 (1) ; Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. See “About Code Examples” on page RXB[7:0] TXB[7:0] R/W R/W R/W R ATmega16( UDR (Read) UDR (Write) R/W R/W R/W R 163 ...

Page 164

... This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effectively dou- bling the transfer rate for asynchronous communication. 2466T–AVR–07/ RXC TXC UDRE FE DOR R R ATmega16( U2X MPCM UCSRA R R R/W R 164 ...

Page 165

... RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. 2466T–AVR–07/10 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN TXEN R/W R/W R/W R ATmega16(L) 161 UCSZ2 RXB8 TXB8 UCSRB R/W R 165 ...

Page 166

... UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity USBS 0 1 ATmega16( USBS UCSZ1 UCSZ0 UCPOL UCSRC R/W R/W R/W R Stop Bit(s) 1-bit 2-bit “Accessing 166 ...

Page 167

... TxD Pin) Rising XCK Edge Falling XCK Edge URSEL – – – UBRR[7: R R/W R/W R/W R ATmega16(L) UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge UBRR[11: ...

Page 168

... Kbps ATmega16(L) Table “Asynchronous Operational ⎞ Closest Match • 100% – ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0. ...

Page 169

... Kbps ATmega16( 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...

Page 170

... Mbps 691.2 Kbps ATmega16(L) MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0. ...

Page 171

... Mbps 1.152 Mbps ATmega16( 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...

Page 172

... Device 1 Device 3 Device 2 Description The device that initiates and terminates a transmission. The Master also generates the SCL clock. The device addressed by a Master. The device placing data on the bus. The device reading data from the bus. ATmega16( ........ R1 R2 Device n 172 ...

Page 173

... START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. 2466T–AVR–07/10 Figure 76, both bus lines are connected to the positive supply voltage through “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega16(L) 294. Two Data Stable 173 ...

Page 174

... Slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 79. Address Packet Format SDA SCL 2466T–AVR–07/10 START STOP START Addr MSB 1 2 START ATmega16(L) REPEATED START STOP Addr LSB R/W ACK 174 ...

Page 175

... Data MSB 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted Addr MSB Addr LSB R/W ACK START SLA+R/W ATmega16(L) Data LSB ACK STOP, REPEATED Data Byte START or Next Data MSB Data LSB ACK ...

Page 176

... If several Masters are trying to address the same Slave, arbitration will continue into the data packet. 2466T–AVR–07/10 TA low SCL from Master A SCL from Master B SCL bus Line TB low Masters Start Counting Low Period ATmega16(L) TA high TB high Masters Start Counting High Period 176 ...

Page 177

... SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 2466T–AVR–07/10 START SDA from Master A SDA from Master B SDA Line SCL Line ATmega16(L) Master A Loses Arbitration, SDA SDA A 177 ...

Page 178

... Address Register (TWAR) Address Comparator SCL frequency Note: Pull-up resistor values should be selected according to the SCL frequency and the capaci- tive bus line load. See Table 120 on page 294 ATmega16(L) Figure 84. All registers drawn SDA Spike Filter Bit Rate Generator Prescaler ...

Page 179

... After the TWI has been addressed by own Slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition 2466T–AVR–07/10 ATmega16(L) 179 ...

Page 180

... TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 R/W R/W R/W R for calculating bit rates TWINT TWEA TWSTA TWSTO TWWC R/W R/W R/W R ATmega16( TWBR2 TWBR1 TWBR0 TWBR R/W R/W R/W R “Bit Rate Generator TWEN – TWIE TWCR R R 180 ...

Page 181

... Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. 2466T–AVR–07/ TWS7 TWS6 TWS5 TWS4 TWS3 ATmega16( – TWPS1 TWPS0 TWSR R R R/W R 181 ...

Page 182

... Rate Generator Unit” on page TWD7 TWD6 TWD5 TWD4 R/W R/W R/W R TWA6 TWA5 TWA4 TWA3 R/W R/W R/W R ATmega16(L) Prescaler Value 178. The value of TWPS1.. TWD3 TWD2 TWD1 TWD0 TWDR R/W R/W R/W R TWA2 TWA1 TWA0 TWGCE R/W R/W ...

Page 183

... TWCR, making sure that TWINT is written to one SLA TWINT set. Status code indicates SLA+W sent, ACK received ATmega16(L) 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...

Page 184

... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. 2466T–AVR–07/10 ATmega16(L) 184 ...

Page 185

... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega16(L) Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits ...

Page 186

... TWINT Flag is set. The numbers in Table 74 to Table 77. Note that the prescaler bits are masked to zero in 86). In order to enter a Master mode, a START condition must be transmitted. The Device 1 Device 2 Device 3 MASTER SLAVE TRANSMITTER RECEIVER ATmega16( ........ Device 186 ...

Page 187

... TWINT TWEA TWSTA TWSTO Application Software Response To TWCR To/from TWDR STO TWINT STA 0 1 Load SLA Load SLA Load SLA+R 0 ATmega16(L) TWWC TWEN – TWIE Table 74). In order to enter MT mode, TWWC TWEN – TWIE TWWC TWEN – TWIE TWWC TWEN – ...

Page 188

... No TWDR action TWDR action TWDR action 1 ATmega16(L) X Data byte will be transmitted and ACK or NOT ACK will be received X Repeated START will be transmitted X STOP condition will be transmitted and TWSTO Flag will be Reset X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be Reset ...

Page 189

... MT S SLA W A $08 $ $38 A $68 $78 DATA From master to slave From slave to master 88). In order to enter a Master mode, a START condition must be transmitted. The ATmega16(L) DATA A P $28 R SLA S $ $30 Other master Other master continues continues $38 Other master ...

Page 190

... Received data can be read from the TWDR Register when the TWINT Flag TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA TWSTO Application Software Response To TWCR To/from TWDR STO TWINT STA ATmega16( ........ Device TWWC TWEN – TWIE Table 74). In order to enter MR mode, TWWC TWEN – TWIE X 1 ...

Page 191

... Other master A continues $68 $78 $B0 DATA From master to slave From slave to master n ATmega16(L) X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to masTer Transmitter mode X Two-wire Serial Bus will be released and not addressed ...

Page 192

... All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 Device 3 SLAVE MASTER RECEIVER TRANSMITTER TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATmega16( ........ Device n R1 TWA2 TWA1 TWA0 TWWC TWEN – TWGCE TWIE X Table 76 ...

Page 193

... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 2466T–AVR–07/10 ATmega16(L) 193 ...

Page 194

... No action ATmega16(L) TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned ...

Page 195

... DATA From master to slave From slave to master 92). All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 SLAVE MASTER TRANSMITTER RECEIVER TWA6 TWA5 TWA4 Device’s Own Slave Address ATmega16(L) A DATA A DATA $60 $80 $80 $88 A $68 A DATA A ...

Page 196

... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 2466T–AVR–07/10 TWINT TWEA TWSTA TWSTO ATmega16(L) TWWC TWEN – TWIE Table 77. The 196 ...

Page 197

... No TWDR action TWDR action TWDR action 1 ATmega16(L) TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...

Page 198

... From master to slave From slave to master n Application Software Response To TWCR To/from TWDR STO TWINT STA No TWDR action No TWCR action TWDR action 0 ATmega16(L) DATA A DATA $B8 $C0 A All 1's $C8 Any number of data bytes A and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus ...

Page 199

... Figure 95. An Arbitration Example SDA SCL 2466T–AVR–07/10 Master Transmitter SLA+W A ADDRESS REPEATED START Transmitted from Master to Slave Device 1 Device 2 Device 3 MASTER SLAVE MASTER TRANSMITTER RECEIVER TRANSMITTER ATmega16(L) Master Receiver Rs SLA+R A DATA Transmitted from Slave to Master V CC ........ Device STOP R2 199 ...

Page 200

... Yes Write 68/78 Direction Read B0 ATmega16(L) Data STOP TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned ...

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