ATMEGA16-16MQ Atmel, ATMEGA16-16MQ Datasheet - Page 274

• Manufacturer Part Number: ATMEGA16-16MQ
• Description: MCU AVR 16K FLASH 16MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16MQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Serial
Programming
Algorithm
2466T–AVR–07/10
Figure 136. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-
tion. The Chip Erase operation turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega16, data is clocked on the rising edge of SCK.
When reading data from the ATmega16, data is clocked on the falling edge of SCK. See
138
To program and verify the ATmega16 in the SPI Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming
3. The SPI Serial Programming instructions will not work if the communication is out of syn-
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte ($53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
for timing details.
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
-0.3V < AVCC < V
MOSI
MISO
SCK
CC
and GND while RESET and SCK are set to “0”. In some sys-
ck
CC
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+0.3V, however, AVCC should always be within 2.7V - 5.5V
PB5
PB6
PB7
XTAL1
RESET
GND
(1)
AVCC
VCC
+2.7 - 5.5V
+2.7 - 5.5V
Figure 116 on page
ck
ck
(2)
ATmega16(L)
≥ 12 MHz
≥ 12 MHz
276):
Figure
274