ATMEGA16-16MQ Atmel, ATMEGA16-16MQ Datasheet - Page 74

MCU AVR 16K FLASH 16MHZ 44-QFN

ATMEGA16-16MQ

Manufacturer Part Number
ATMEGA16-16MQ
Description
MCU AVR 16K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA16-16MQ

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Force Output
Compare
Compare Match
Blocking by TCNT0
Write
Using the Output
Compare Unit
Compare Match
Output Unit
2466T–AVR–07/10
The OCR0 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled
the CPU will access the OCR0 directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0) bit. Forcing compare match will not set the
OCF0 Flag or reload/clear the timer, but the OC0 pin will be updated as if a real compare match
had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled).
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized
to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the output compare unit, inde-
pendently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals
the OCR0 value, the compare match will be missed, resulting in incorrect waveform generation.
Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.
The setup of the OC0 should be performed before setting the Data Direction Register for the port
pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare
(FOC0) strobe bits in Normal mode. The OC0 Register keeps its value even when changing
between waveform generation modes.
Be aware that the COM01:0 bits are not double buffered together with the compare value.
Changing the COM01:0 bits will take effect immediately.
The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses
the COM01:0 bits for defining the Output Compare (OC0) state at the next compare match. Also,
the COM01:0 bits control the OC0 pin output source.
the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the fig-
ure are shown in bold. Only the parts of the general I/O port Control Registers (DDR and PORT)
that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference
is for the internal OC0 Register, not the OC0 pin. If a System Reset occur, the OC0 Register is
reset to “0”.
Figure 30
shows a simplified schematic of
ATmega16(L)
74

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