ATMEGA3250P-20AUR Atmel, ATMEGA3250P-20AUR Datasheet
ATMEGA3250P-20AUR
Specifications of ATMEGA3250P-20AUR
Available stocks
Related parts for ATMEGA3250P-20AUR
ATMEGA3250P-20AUR Summary of contents
Page 1
... I/O and Packages – 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega325PV/ATmega3250PV MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega325P/3250P MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
Page 2
... Pin Configurations Figure 1-1. ATmega325P/3250P 2 Pinout ATmega3250P DNC 1 2 (RXD/PCINT0) PE0 INDEX CORNER (TXD/PCINT1) PE1 3 4 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 5 6 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 7 8 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 9 10 VCC GND 11 12 DNC (PCINT24) PJ0 13 14 (PCINT25) PJ1 DNC ...
Page 3
Figure 1-2. Note: 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. ...
Page 4
Block Diagram Figure 2-1. Block Diagram GND VCC DATA REGISTER PORTF AVCC AGND AREF JTAG TAP ON-CHIP DEBUG BOUNDARY- SCAN PROGRAMMING LOGIC USART DATA REGISTER PORTE The AVR core combines a rich instruction set with 32 general purpose working ...
Page 5
... The ATmega325P/3250P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between ATmega325P and ATmega3250P The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. 2-1 on page 5 Table 2-1. Device ATmega325P ATmega3250P 8023F– ...
Page 6
Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...
Page 7
... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250P as listed on page 75. ...
Page 8
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characterizations” on page 2.3.13 XTAL1 ...
Page 9
... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8023F–AVR–07/09 ATmega325P/3250P 9 ...
Page 10
Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code ...
Page 11
AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
Page 12
ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...
Page 13
AVR Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register ...
Page 14
Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C ...
Page 15
The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
Page 16
SPH and SPL – Stack Pointer High and Stack Pointer Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven ...
Page 17
Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be ...
Page 18
CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 C Code Example char ...
Page 19
AVR Memories 7.1 Overview This section describes the different memories in the ATmega325P/3250P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega325P/3250P features an EEPROM Memory for data ...
Page 20
Figure 7-1. 7.3 SRAM Data Memory Figure 7-2 The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O ...
Page 21
The Register File is described in page 14. Figure 7-2. 7.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk ...
Page 22
The write access time for the EEPROM is given in lets the user software detect when the next byte can be written. If the user code contains instruc- tions that write the EEPROM, some precautions must be taken. In heavily ...
Page 23
Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to ...
Page 24
EECR – The EEPROM Control Register Bit 0x1F (0x3F) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing ...
Page 25
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is ...
Page 26
Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write ...
Page 27
Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 7.6.4 General Purpose I/O Registers The ATmega325P/3250P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly ...
Page 28
GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value ATmega325P/3250P MSB R/W R/W R/W R LSB R/W R/W R/W R ...
Page 29
System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
Page 30
Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...
Page 31
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. C1 and C2 should always be ...
Page 32
Table 8-4. CKSEL0 Notes: 8.5 Low-frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be ...
Page 33
The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111” as shown in Table 8-6. Table 8-6. SUT1.. Table 8-7. CKSEL3..0 0110 0111 Note: 8.6 Calibrated Internal RC Oscillator By ...
Page 34
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-9 on page Table 8-9. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 8.7 External Clock To drive the device ...
Page 35
It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to ...
Page 36
Register Description 8.11.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...
Page 37
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within ...
Page 38
Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the ...
Page 39
BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for some ...
Page 40
Power-down Mode When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the ...
Page 41
Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
Page 42
Refer to the section which pins are enabled. If the input buffer is enabled and the input signal is left floating or have ...
Page 43
Register Description 9.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...
Page 44
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared ...
Page 45
System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
Page 46
Figure 10-1. Reset Logic BODLEVEL [1..0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ever well as to detect a failure in supply voltage. ...
Page 47
Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is ...
Page 48
Figure 10-5. Brown-out Reset During Operation 10.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out ...
Page 49
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 10.4 Watchdog Timer The Watchdog Timer is clocked from a ...
Page 50
In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same ...
Page 51
WDTCR – Watchdog Timer Control Register Bit (0x60) Read/Write Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must ...
Page 52
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly ...
Page 53
Interrupts 11.1 Overview ...
Page 54
... Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 3. PCINT2 and PCINT3 are only present in ATmega3250P and ATmega6450P. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement ...
Page 55
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general ...
Page 56
Address Labels Code ; .org 0x3800/0x7800 0x3800/0x7800 0x3802/0x7802 0x3804/0x7804 ... 0x382C/0x782C ; 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 0x382F/0x782F 0x3830/0x7830 0x3831/0x7831 0x3832/0x7832 0x3833/0x7833 11.2.1 Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector ...
Page 57
Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
Page 58
... Clock and Clock Options” on page Notes: 8023F–AVR–07/09 ”EICRA – External Interrupt Control Register A” on page 1. PCMSK3 and PCMSK2 are only present in ATmega3250P. 2. PCINT30:16 are only present in ATmega3250P. Only PCINT15:0 are present in ATmega325P. See ”Pin Configurations” on page 2 ATmega325P/3250P (1) ...
Page 59
Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 12-1. Pin Change Interrupt 12.3 Register Description 12.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains ...
Page 60
Table 12-1. ISC01 12.3.2 EIMSK – External Interrupt Mask Register Bit (0xD1) Read/Write Initial Value • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in ...
Page 61
EIFR – External Interrupt Flag Register Bit 0x1C (0x3C) Read/Write Initial Value • Bit 7 – PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If ...
Page 62
... I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8023F–AVR–07/09 ( – PCINT30 PCINT29 PCINT28 R R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R PCMSK3 and PCMSK2 are only present in ATmega3250P PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega325P/3250P ...
Page 63
I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
Page 64
Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ...
Page 65
The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...
Page 66
Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
Page 67
Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...
Page 68
Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
Page 69
Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...
Page 70
... AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. Some pins are connected to different LCS segments on ATmega325P and ATmega3250P. See pinout on ATmega325P/3250P 70 ...
Page 71
Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • OC2A/PCINT15, Bit 7 OC2, ...
Page 72
PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt source. • MISO/PCINT11 – Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a ...
Page 73
Table 13-4 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 13-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-5. Signal Name PUOE PUOV DDOE ...
Page 74
Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-6. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • INT0 – Port D, ...
Page 75
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-8. Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit 7 PCINT7, Pin Change Interrupt Source ...
Page 76
XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 oper- ates in ...
Page 77
Table 13-10. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 13.3.4 Alternate Functions of Port F The Port F has an alternate function as analog input for ...
Page 78
TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be ...
Page 79
Table 13-13. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.5 Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-14. Port G Pins ...
Page 80
... DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.6 Alternate Functions of Port H Port H is only present in ATmega3250P. The alternate pin configuration is as follows: Table 13-16. Port H Pins Alternate Functions Port Pin PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 The alternate pin configuration is as follows: • ...
Page 81
PCINT20 – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. • PCINT19– Port H, Bit 3 PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve ...
Page 82
... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port J Port J is only present in ATmega3250P. The alternate pin configuration is as follows: Table 13-19. Port J Pins Alternate Functions Port Pin PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 The alternate pin configuration is as follows: • ...
Page 83
PCINT27 – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. • PCINT26 – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can ...
Page 84
Table 13-21. Overriding Signals for Alternate Functions in PH3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega325P/3250P 84 PJ3/PCINT27 PJ2/PCINT26 – – ...
Page 85
Register Description 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...
Page 86
PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...
Page 87
PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 13.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 13.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write Initial ...
Page 88
... PORTJ6 PORTJ5 PORTJ4 R R – DDJ6 DDJ5 R R – PINJ6 PINJ5 R R/W R/W 0 N/A N/A 1. Register only available in ATmega3250P DDH4 DDH3 DDH2 DDH1 R/W R/W R/W R PINH3 PINH2 PINH1 R/W R/W R/W R/W N/A N/A N/A N PORTJ3 PORTJ2 PORTJ1 ...
Page 89
... T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 8023F–AVR–07/09 ”Pinout ATmega3250P” on page 2 TCCRn count clear ...
Page 90
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output ...
Page 91
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer ...
Page 92
Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. ...
Page 93
Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear ...
Page 94
Figure 14-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out- put) ...
Page 95
Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...
Page 96
The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the ...
Page 97
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to ...
Page 98
Figure 14-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
Page 99
BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare ...
Page 100
Figure 7 Figure 7. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f /8) clk_I/O clk clk (clk I/O TCNTn (CTC) OCRnx OCFnx 14.9 Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but ...
Page 101
The edge detector generates one clk (CSn2 edge it detects. Figure 14-8. T1/T0 Pin Sampling Tn The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied ...
Page 102
Register Description 14.10.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, ...
Page 103
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-3. COM0A1 Table 14-4 mode. Table 14-4. ...
Page 104
Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 14-6. CS02 external pin modes are used for ...
Page 105
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding ...
Page 106
Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that ...
Page 107
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM1 bit in enable the Timer/Counter1 module. 8023F–AVR–07/09 ”Pinout ATmega3250P” on page ”Register Description” on page 128. ”PRR – Power Reduction Register” on page 44 ATmega325P/3250P Figure 15-1 ...
Page 108
Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
Page 109
Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICP1) ...
Page 110
Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...
Page 111
The following code examples show how atomic read of the TCNT1 Register contents. Reading any ...
Page 112
The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt ...
Page 113
Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
Page 114
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
Page 115
TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written ...
Page 116
I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares ...
Page 117
PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer ...
Page 118
Secondly the COM1x1:0 bits control the OC1x pin output source. schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the ...
Page 119
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 15.9 Modes ...
Page 120
Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...
Page 121
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...
Page 122
When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next ...
Page 123
OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...
Page 124
TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...
Page 125
OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
Page 126
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
Page 127
Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
Page 128
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 ...
Page 129
Table 15-3 PWM mode. Table 15-3. COM1A1/COM1B1 Note: Table 15-4 correct or the phase and frequency correct, PWM mode. Table 15-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B ...
Page 130
Figure 15-14. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
Page 131
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
Page 132
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 15.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...
Page 133
ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...
Page 134
Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, ...
Page 135
... I/O pins, refer to I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 16-1. 8-bit Timer/Counter Block Diagram 8023F–AVR–07/09 ”Pinout ATmega3250P” on page ”Register Description” on page 149. TCCRnx count ...
Page 136
Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask ...
Page 137
Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 16-2 shows a block diagram of the counter and its surrounding environment. Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): count direction ...
Page 138
Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page Figure 16-3 Figure 16-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the ...
Page 139
Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of whether ...
Page 140
The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out- put) is still controlled by the Data Direction ...
Page 141
Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the ...
Page 142
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21 provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter ...
Page 143
The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating ...
Page 144
Figure 16-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
Page 145
BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare ...
Page 146
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn Figure 16-11 Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn ATmega325P/3250P 146 clk I/O clk Tn /8) I/O OCRnx - ...
Page 147
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching ...
Page 148
Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, ...
Page 149
TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. If applying an external clock on TOSC1, the EXCLK bit in ...
Page 150
Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O ...
Page 151
Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 16-6. Table 16-6. CS22 16.10.2 TCNT2 – Timer/Counter Register ...
Page 152
Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) ...
Page 153
Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an ...
Page 154
SPI – Serial Peripheral Interface 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
Page 155
The interconnection between Master and Slave CPUs with SPI is shown in 155. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin ...
Page 156
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 17-1. Pin MOSI MISO SCK SS Note: 8023F–AVR–07/09 Table 17-1. For more details on automatic port ...
Page 157
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
Page 158
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8023F–AVR–07/09 (1) ; ...
Page 159
SS Pin Functionality 17.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
Page 160
Figure 17-3. SPI Transfer Format with CPHA = 0 Figure 17-4. SPI Transfer Format with CPHA = 1 17.5 Register Description 17.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt ...
Page 161
Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit ...
Page 162
Table 17-4. SPI2X 17.5.2 SPSR – SPI Status Register Bit 0x2D (0x4D) Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE ...
Page 163
USART0 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...
Page 164
Figure 18-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...
Page 165
Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as ...
Page 166
Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to The USART Baud Rate Register ...
Page 167
Figure 18-3. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRRn Some examples of UBRRn values for some system ...
Page 168
Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...
Page 169
St ( IDLE be The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of ...
Page 170
For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: ; Set baud rate out out ; Enable receiver and transmitter ldi out ; Set frame format: 8data, 2stop ...
Page 171
Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by ...
Page 172
Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following ...
Page 173
Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) ...
Page 174
UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSR0A, RXC0 rjmp ...
Page 175
The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example ...
Page 176
Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
Page 177
The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read ...
Page 178
Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 18-6. Start Bit Sampling Sample (U2X = 0) Sample ...
Page 179
Figure 18-8. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
Page 180
Table 18-1. # (Data+Parity Bit) Table 18-2. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
Page 181
When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...
Page 182
Register Description 18.10.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
Page 183
Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn ...
Page 184
Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt ...
Page 185
Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
Page 186
Figure 18-13. UCPOLn Bit Settings 18.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers n Bit Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must ...
Page 187
Table 18-3. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2Xn = 0 Rate (bps) UBRRn Error UBRRn 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 14.4k 3 8.5% ...
Page 188
Table 18-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
Page 189
Table 4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
Page 190
Table 5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
Page 191
... Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 8023F–AVR–07/09 ”Pinout ATmega3250P” on page 2 ”Register Descriptions” on page ...
Page 192
The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count ...
Page 193
Figure 19-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK The Three-wire mode timing is shown in Figure 19-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Shift Register (USIDR) ...
Page 194
The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is ...
Page 195
SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
Page 196
Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim- iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 19-4. ...
Page 197
Figure 19-5. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram (Figure 19-5.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while ...
Page 198
Start Condition Detector The start condition detector is shown in to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and ...
Page 199
Register Descriptions 19.5.1 USIDR – USI Data Register Bit (0xBA) Read/Write Initial Value The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register (USIDR) the Serial Register is accessed directly serial clock ...
Page 200
Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is ...