ATMEGA329V-8MU Atmel, ATMEGA329V-8MU Datasheet - Page 243

• Manufacturer Part Number: ATMEGA329V-8MU
• Description: IC AVR MCU 32K 8MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.4
2552K–AVR–04/11
LCDCCR – LCD Contrast Control Register
• Bits 7:5 – LCDDC2:0: LDC Display Configuration
The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD
clock period, even if the selected drive time is longer. When using static duty or blanking, drive
time will always be one half prescaled LCD clock period.
New values take effect immediately, and can cause small glitches in the display output. This can
be avoided by setting the LCDBL in LCDCRA, and wait to the next start of frame before chang-
ing LCDDC2:0.
Table 23-7.
Note:
• Bit 4 – Reserved Bit
This bit is reserved in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 3:0 – LCDCC3:0: LCD Contrast Control
The LCDCC3:0 bits determine the maximum voltage V
different selections are shown in
frame.
Table 23-8.
Bit
(0xE7)
Read/Write
Initial Value
LCDCC3
LCDDC2
0
0
0
0
The drive time will be longer dependent on oscillator startup time.
0
0
0
0
1
1
1
1
LCDDC2
R/W
7
0
LCD Display Configuration
LCD Contrast Control
LCDCC2
LCDDC1
0
0
0
0
R/W
6
0
LCDDC1
0
0
1
1
0
0
1
1
LCDDC0
R/W
5
0
LCDCC1
Table
0
0
1
1
R
4
0
23-8. New values take effect every beginning of a new
–
LCDDC0
ATmega329/3290/649/6490
LCDCC3
LCDCC0
0
1
0
1
0
1
0
1
R/W
3
0
0
1
0
1
LCDCC2
LCD
R/W
2
0
on segment and common pins. The
Maximum Voltage V
Nominal drive time
300µs
70µs
150µs
450µs
575µs
850µs
1150µs
50% of clk
LCDCC1
R/W
0
1
2.60
2.65
2.70
2.75
LCDCC0
LCD_PS
R/W
0
0
LCDCCR
LCD
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