ATMEGA329V-8MU Atmel, ATMEGA329V-8MU Datasheet - Page 32

• Manufacturer Part Number: ATMEGA329V-8MU
• Description: IC AVR MCU 32K 8MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.8
8.9
8.9.1
8.10
8.10.1
32
Timer/Counter Oscillator
System Clock Prescaler
Register Description
ATmega329/3290/649/6490
Switching Time
OSCCAL – Oscillator Calibration Register
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output when the CKOUT Fuse is programmed.
ATmega329/3290/649/6490 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with
XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the
calibrated internal RC Oscillator is selected as system clock source. The Oscillator is optimized
for use with a 32.768kHz watch crystal. See
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See
description on selecting external clock as input instead of a 32kHz crystal.
The ATmega329/3290/649/6490 system clock can be divided by setting the Clock Prescale
Register – CLKPR. This feature can be used to decrease power consumption when the require-
ment for processing power is low. This can be used with all clock source options, and it will affect
the clock frequency of the CPU and all synchronous peripherals. clk
FLASH
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
2 on page
Bit
(0x66)
Read/Write
Initial Value
are divided by a factor as shown in
329. Calibration outside that range is not guaranteed.
Table 28-2 on page
CAL7
R/W
7
CAL6
R/W
6
“Asynchronous Operation of Timer/Counter2” on page 151
CAL5
R/W
5
329. The application software can write this register to change
Device Specific Calibration Value
CAL4
R/W
4
Table 8-11 on page
Figure 8-2 on page 28
CAL3
R/W
3
CAL2
R/W
2
34.
CAL1
R/W
1
for crystal connection.
I/O
, clk
CAL0
R/W
0
ADC
, clk
OSCCAL
2552K–AVR–04/11
CPU
for further
Table 28-
, and clk-