ATMEGA329V-8MU Atmel, ATMEGA329V-8MU Datasheet - Page 95

• Manufacturer Part Number: ATMEGA329V-8MU
• Description: IC AVR MCU 32K 8MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.1
14.5.2
14.5.3
14.6
2552K–AVR–04/11
Compare Match Output Unit
Force Output Compare
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is
disabled the CPU will access the OCR0A directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the
OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare
match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or
toggled).
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-
ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the Output Compare unit,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
counting down.
The setup of the OC0A should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-
pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare value.
Changing the COM0A1:0 bits will take effect immediately.
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator
uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare
match. Also, the COM0A1:0 bits control the OC0A pin output source.
plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits,
and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-
ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the
OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System
Reset occur, the OC0A Register is reset to “0”.
ATmega329/3290/649/6490
Figure 14-4
shows a sim-
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