AT32UC3L064-D3HR Atmel, AT32UC3L064-D3HR Datasheet
AT32UC3L064-D3HR
Specifications of AT32UC3L064-D3HR
Available stocks
Related parts for AT32UC3L064-D3HR
AT32UC3L064-D3HR Summary of contents
Page 1
... SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADC) with Bits Resolution – Internal Temperature Sensor ® ® 32-bit AVR Microcontroller 2 C-compatible ® 32-bit AVR Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary 32099F–11/2010 ...
Page 2
... Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module ® – Hardware Assisted Atmel AVR – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors • QTouch Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch and QMatrix Acquisition • ...
Page 3
... Description The Atmel AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 high-perfor- mance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con- troller for supporting modern operating systems and real-time operating systems ...
Page 4
... One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key Suppression QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications ...
Page 5
Overview 2.1 Block Diagram Figure 2- 32099F–11/2010 Block Diagram MCKO MDO[5..0] MSEO[1..0] EVTI_N NEXUS EVTO_N CLASS 2+ TCK JTAG OCD TDO INTERFACE TDI TMS DATAOUT aWire RESET_N M S/M SAU S CONFIGURATION HSB-PB BRIDGE B POWER MANAGER ...
Page 6
... Temperature Sensor Analog Comparators Capacitive Touch Module JTAG aWire Max Frequency Packages 32099F–11/2010 Configuration Summary AT32UC3L064 64KB 16KB Digital Frequency Locked Loop 40-150MHz (DFLL) Crystal Oscillator 3-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) ...
Page 7
Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099F–11/2010 TQFP48/QFN48 Pinout ...
Page 8
Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099F–11/2010 TLLGA48 Pinout AT32UC3L016/32/64 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND ...
Page 9
Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G P ...
Page 10
Table 3-1. GPIO Controller Function Multiplexing Normal 40 PA19 19 VDDIO I/O Normal 25 PA20 20 VDDIN I/O Normal I/O (TWI, 24 PA21 21 VDDIN 5V tolerant SMBus) Normal 9 PA22 22 VDDIO I/O Normal 6 PB00 32 VDDIO I/O ...
Page 11
Refer to the of the TWI, 5V Tolerant, and SMBUS pins. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed ...
Page 12
Table 3-4. Pin MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the ...
Page 13
Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function ACAN3 - ACAN0 Negative inputs for comparators "A" ACAP3 - ACAP0 Positive inputs for comparators "A" ACBN3 - ...
Page 14
Table 3-7. Signal Descriptions List TMS Test Mode Select RESET_N Reset PWMA35 - PWMA0 PWMA channel waveforms PWMAOD35 - PWMA channel waveforms, open drain PWMAOD0 mode GCLK4 - GCLK0 Generic Clock Output RC32OUT RC32K output at startup XIN0 Crystal 0 ...
Page 15
Table 3-7. Signal Descriptions List Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data TXD Transmit Data Note: 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description ...
Page 16
I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up ...
Page 17
RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be ...
Page 18
Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
Page 19
The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some ...
Page 20
Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
Page 21
Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
Page 22
Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d 4.3.2.5 Unimplemented Instructions ...
Page 23
Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
Page 24
Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
Page 25
Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
Page 26
Table 4-3. Reg # 33- ...
Page 27
Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
Page 28
EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
Page 29
Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
Page 30
An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
Page 31
Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
Page 32
... Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...
Page 33
Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE0400 0xFFFE0800 0xFFFF0000 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32099F–11/2010 Peripheral Name FLASHCDW Flash Controller - FLASHCDW HMATRIX HSB Matrix - ...
Page 34
Table 5-3. Peripheral Address Mapping 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being ...
Page 35
The following GPIO registers are mapped on the local bus: Table 5-4. Port 0 1 32099F–11/2010 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) ...
Page 36
Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3L has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is ...
Page 37
Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). ...
Page 38
Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.62-1.98V ...
Page 39
Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in use Shutdown mode. Figure 6-4. In ...
Page 40
Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise ...
Page 41
Electrical Characteristics 7.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 7.2 Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C Storage temperature...................................... -60°C to +150°C Voltage on ...
Page 42
Table 7-3. Symbol V VDDIO V VDDIN V VDDCORE V VDDANA Note: 7.4 Maximum Clock Frequencies These parameters are given in the following conditions: • V VDDCORE • Temperature = -40°C to 85°C Table 7-4. Symbol f CPU f PBA ...
Page 43
Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details tor static current • Operating conditions external core supply – V – Corresponds to the 1.8V ...
Page 44
Table 7-5. Power Consumption for Different Operating Modes Mode Conditions -CPU running a recursive Fibonacci algorithm (1) Active -CPU running a division algorithm (1) Idle (1) Frozen (1) Standby Stop DeepStop -OSC32K and AST stopped -Internal core supply -OSC32K running ...
Page 45
Figure 7-2. 7.5.1 Peripheral Power Consumption The values in conditions. • Operating conditions internal core supply – V – V – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations ...
Page 46
Table 7-6. Peripheral ACIFB ADCIFB AST AW USART CAT EIC FREQM GLOC GPIO PWMA SPI TC TWIM TWIS USART WDT Notes: 32099F–11/2010 Typical Current Consumption by Peripheral (1) 1. Includes the current consumption on VDDANA and ADVREFP. 2. These ...
Page 47
I/O Pin Characteristics Table 7-7. Normal I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP V Input low-level voltage IL V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage OH (2) f Output frequency ...
Page 48
Table 7-8. High-drive I/O Pin Characteristics Symbol Parameter V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage OH Output frequency, all High- f drive I/O pins, except MAX (2) PA08 and PA09 Rise time, all ...
Page 49
Table 7-9. High-drive I/O, 5V Tolerant, Pin Characteristics Symbol Parameter V Output high-level voltage OH (2) f Output frequency MAX (2) t Rise time RISE (2) t Fall time FALL I Input leakage current LEAK C Input capacitance IN Notes: ...
Page 50
Oscillator Characteristics 7.7.1 Oscillator 0 (OSC0) Characteristics 7.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 7-11. Digital Clock Characteristics Symbol Parameter f XIN clock frequency ...
Page 51
Figure 7-3. UC3L 7.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 7-3 must choose a crystal oscillator where the crystal load capacitance C in the table. The exact value of C Table 7-13. 32 KHz Crystal Oscillator Characteristics Symbol Parameter f ...
Page 52
Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14. Digital Frequency Locked Loop Characteristics Symbol Parameter (2) f Output frequency OUT f Reference frequency REF FINE resolution Frequency drift over voltage and temperature (2) Accuracy I Power consumption DFLL (2) ...
Page 53
Figure 7-4. DFLL Open Loop Frequency Variation 160 150 140 130 120 110 100 90 80 -40 -20 Note: 1. The plot shows a typical behaviour for coarse = 99 and fine = 255 in open loop mode. 7.7.4 120MHz ...
Page 54
RC Oscillator (RC32K) Characteristics Table 7-16. 32kHz RC Oscillator Characteristics Symbol Parameter (1) f Output frequency OUT I Current consumption RC32K t Startup time STARTUP Note: 1. These values are based on simulation and characterization of other AVR ...
Page 55
Table 7-20. Flash Endurance and Data Retention Symbol Parameter N Array endurance (write/page) FARRAY N General Purpose fuses endurance (write/bit) FFUSE t Data retention RET 7.9 Analog Characteristics 7.9.1 Voltage Regulator Characteristics Table 7-21. VREG Electrical Characteristics Symbol Parameter V ...
Page 56
Power-on Reset 18 Characteristics Table 7-23. POR18 Characteristics Symbol Parameter V Voltage threshold on V POT+ V Voltage threshold on V POT- t Detection time DET Figure 7-5. V POT+ V POT- 32099F–11/2010 Condition rising VDDCORE falling VDDCORE Time ...
Page 57
Power-on Reset 33 Characteristics Table 7-24. POR33 Characteristics Symbol Parameter V Voltage threshold on V POT+ V Voltage threshold on V POT- t Detection time DET I Current consumption POR33 t Startup time STARTUP Figure 7-6. V POT+ V ...
Page 58
Table 7-26. BOD Characteristics Symbol Parameter V BOD hysteresis HYST t Detection time DET I Current consumption BOD t Startup time STARTUP 7.9.5 Supply Monitor 33 Characteristics Table 7-27. SM33 Characteristics Symbol Parameter V Voltage threshold TH Step size, between ...
Page 59
Analog to Digital Converter Characteristics Table 7-28. ADC Characteristics Symbol Parameter f ADC clock frequency ADC t Startup time STARTUP t Conversion time (latency) CONV Throughput rate V Reference voltage range ADVREFP I Current consumption on V ADC Current ...
Page 60
Figure 7- The minimum sample and hold time (in ns) can be found using this formula: t SAMPLEHOLD Where n is the number of bits in the conversion. ADCIFB ACR register. Please refer to the ADCIFB chapter for ...
Page 61
Temperature Sensor Characteristics Table 7-32. Temperature Sensor Characteristics Symbol Parameter Gradient I Current consumption TS t Startup time STARTUP Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy. ...
Page 62
Capacitive Touch Characteristics 7.9.9.1 Discharge Current Source Table 7-34. DICS Characteristics Symbol Parameter R Internal resistor REF k Trim step size 7.9.9.2 Strong Pull-up Pull-down Table 7-35. Strong Pull-up Pull-down Parameter Pull-down resistor Pull-up resistor 32099F–11/2010 AT32UC3L016/32/64 Min Typ ...
Page 63
Timing Characteristics 7.10.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula CONST Where another clock source than RCSYS is selected as CPU clock the startup time of ...
Page 64
USART in SPI Mode Timing 7.10.3.1 Master mode Figure 7-8. SPCK MISO MOSI Figure 7-9. SPCK MISO MOSI Table 7-38. USART in SPI Mode Timing, Master Mode Symbol Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold ...
Page 65
Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. ...
Page 66
Figure 7-12. USART in SPI Slave Mode NPCS Timing SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 7-39. USART in SPI mode Timing, Slave Mode Symbol Parameter USPI6 SPCK falling to MISO delay USPI7 MOSI setup time before SPCK rises USPI8 MOSI ...
Page 67
The maximum SPI slave output frequency is given by the following formula: Where the SPI master setup time. Please refer to the SPI master datasheet for maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of ...
Page 68
Table 7-40. SPI Timing, Master Mode Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after ...
Page 69
Figure 7-16. SPI Slave Mode With (CPOL= NCPHA (CPOL= NCPHA= 1) SPCK MISO MOSI Figure 7-17. SPCK, CPOL=0 SPCK, CPOL=1 NPCS Table 7-41. SPI Timing, Slave Mode Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup ...
Page 70
The maximum SPI slave input frequency is given by the following formula: Where CPOL and NCPHA. ter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave output frequency is given by the following ...
Page 71
Table 7-42. TWI-Bus Timing Requirements Symbol Parameter t Data set-up time SU-DAT-TWI t SU-DAT t TWCK LOW period LOW-TWI t LOW t TWCK HIGH period HIGH f TWCK frequency TWCK ≤ f Notes: 1. Standard mode: TWCK 2. A device ...
Page 72
JTAG Timing Figure 7-18. JTAG Interface Signals TMS/TDI Boundary Scan Inputs Boundary Scan Outputs (1) Table 7-43. JTAG Timings Symbol Parameter JTAG0 TCK Low Half-period JTAG1 TCK High Half-period JTAG2 TCK Period JTAG3 TDI, TMS Setup before TCK High ...
Page 73
Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature where: • ...
Page 74
Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32099F–11/2010 AT32UC3L016/32/64 mg MSL3 MS-026 E3 74 ...
Page 75
Figure 8-2. QFN-48 Package Drawing Note: The exposed pad is not connected to anything. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32099F–11/2010 AT32UC3L016/32/64 ...
Page 76
Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32099F–11/2010 AT32UC3L016/32/64 mg MSL3 M0-220 E4 76 ...
Page 77
Soldering Profile Table 8-11 Table 8-11. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature ...
Page 78
... Ordering Information Table 9-1. Ordering Information Device Ordering Code AT32UC3L064-AUTES AT32UC3L064-AUT AT32UC3L064-AUR AT32UC3L064-ZAUES AT32UC3L064 AT32UC3L064-ZAUT AT32UC3L064-ZAUR AT32UC3L064-D3HES AT32UC3L064-D3HT AT32UC3L064-D3HR AT32UC3L032-AUT AT32UC3L032-AUR AT32UC3L032-ZAUT AT32UC3L032 AT32UC3L032-ZAUR AT32UC3L032-D3HT AT32UC3L032-D3HR AT32UC3L016-AUT AT32UC3L016-AUR AT32UC3L016-ZAUT AT32UC3L016 AT32UC3L016-ZAUR AT32UC3L016-D3HT AT32UC3L016-D3HR 32099F–11/2010 Carrier Type Package Package Type ES Tray TQFP 48 Tape & ...
Page 79
Errata 10.1 Rev. E 10.1.1 Processor and Architecture 1. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU ...
Page 80
Solution 2: Only turn off the CFD while running the main clock on RCSYS. 3. Sleepwalking in Idle and Frozen Sleep mode will mask all other PB clocks If the CPU is in Idle or Frozen Sleep mode and a ...
Page 81
Fix / Workaround Disable the interrupt, clear the interrupt by writing a one to GPIO.IFRC, then enable the interrupt. 10.1.8 SPI 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read ...
Page 82
If possible, do not disable the TWIM absolutely necessary to disable the TWIM, there must be a software delay of at least two TWCK periods between the detection of SR.IDLE==1 and the disabling of the TWIM. 2. ...
Page 83
CPU clock speed robustness The aWire memory speed request command counter wraps at ...
Page 84
Rev. D 10.2.1 Processor and Architecture 1. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception ...
Page 85
When entering Shutdown mode while debugging the chip using JTAG or aWire interface. In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control Interface (SCIF) to mask the POR33 reset will be ineffective. Fix/Workaround ...
Page 86
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode directly after the BUSY bit is cleared the ...
Page 87
SR.TDRE bit by writing to TDR the SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is empty, and all data written ...
Page 88
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the asynchronous wake will not occur until the next AST event. For example, if the AST is gen- erating peripheral events to the CAT every ...
Page 89
None 10.2.14 Chip 1. Increased Power Consumption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis- abled, this will lead to an increased power consumption in ...
Page 90
RETS behaves incorrectly when MPU is enabled RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Workaround Make system stack readable in unprivileged mode, or return from ...
Page 91
In the PRAS and PRBS registers MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. 10.4.4 SAU 1. The SR.IDLE ...
Page 92
Disabling POR33 may generate spurious resest Depending on operating conditions, POR33 may generate a spurious reset in one of the fol- lowing cases: - When POR33 is disabled from the user interface. - When SM33 supply monitor is enabled. ...
Page 93
OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and OSCCTRL0.MODE == 0) -A sleep mode where the OSC0 is automatically disabled is entered -The chip enters sleep walking Fix/Workaround Do not run OSC0 in external clock mode ...
Page 94
If max step size is above 7, the DFLL might not lock at the correct frequency if the target fre- quency is below 30MHz. Fix/Workaround If the target frequency is below 30MHz, use max step size (DFLL0MAXSTEP.MAXSTEP ...
Page 95
Fix/Workaround None. 17. RC120MVERSION register reads 0x100 The RC120MVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 18. GCLK5 is non-functional GCLK5 is non-functional. Fix/Workaround None. 19. DFLLIF might loose fine lock when dithering is disabled When dithering is disabled, ...
Page 96
Fix/Workaround None. 3. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi- ately issue ...
Page 97
SPI 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in ...
Page 98
Fix/Workaround Do not write both CR.STREN and CR.SOAM to one if the device needs to wake from deep sleep modes. 4. TWI pins are not SMBus compliant The TWI pins draws current when the pins are supplied with 3.3 V ...
Page 99
Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the SMBAL cannot be used. 10.4.15 PWMA 1. PARAMETER register reads 0x2424 The PARAMETER register reads 0x2424 instead ...
Page 100
ADCIFB 1. Pendetect in sleep modes without CLK_ADCIFB will not wake the system The pendetect will not wake the system from a sleep mode if the clock for the ADCIFB (CLK_ADCIFB) is turned off. Fix/Workaround Use a sleep mode ...
Page 101
CONFW.WEVSRC and CONFW.WEVEN are not correctly described in the user interface CONFW.WEVSRC is only two bits instead of three bits wide. Only values 0, 1, and 2 can be written to this register. CONFW.WEVEN is in bit position 10 ...
Page 102
CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the ...
Page 103
The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the device receives a wakeup either ...
Page 104
Fix/Workaround Swap pins PB01 and PB05 if using OCD AUX1. 5. The JTAG is enabled at power up The JTAG function on pins PA00, PA01, PA02, and PA03, are enabled after startup. Normal I/O module functionality is not possible on ...
Page 105
Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. F- 11/2010 1. 2. 11.2 Rev. E- ...
Page 106
... Ordering Information: Ordering code for TQFP ES changed from AT32UC3L064-AUES to AT32UC3L064-AUTES. TLLGA48 Tray option added. Features and Description: Added QTouch library support. USART: Description of unimplemented features removed. Electrical Characteristics: Power Consumption numbers updated. Flash timing numbers added. Package and Pinout: Added pinout figure for TLLGA48 package. ...
Page 107
Rev. A – 06/2009 1. 32099F–11/2010 ACIFB: CONFW.WEVSRC is bit 8-10, CONFW.EWEVEN is bit 11. CONF.EVENP and CONF.EVENN bits are swapped. CAT: Matrix size not Electrical ...
Page 108
Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 Package and Pinout ................................................................................. 7 4 Processor and Architecture .................................................................. 18 5 Memories ................................................................................................ 32 6 Supply and Startup Considerations ..................................................... 36 7 Electrical Characteristics ...
Page 109
Mechanical Characteristics ................................................................... 73 9 Ordering Information ............................................................................. 78 10 Errata ....................................................................................................... 79 11 Datasheet Revision History ................................................................ 105 Table of Contents....................................................................................... i 32099F–11/2010 7.8 Flash Characteristics .......................................................................................54 7.9 Analog Characteristics .....................................................................................55 7.10 Timing Characteristics .....................................................................................63 8.1 Thermal Considerations ...
Page 110
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...