ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet
ATMEGA3290P-20AUR
Specifications of ATMEGA3290P-20AUR
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ATMEGA3290P-20AUR Summary of contents
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... Peripheral Features – Segment LCD Driver (ATmega329P) – Segment LCD Driver (ATmega3290P) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – ...
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Pin Configurations Figure 1-1. MLF/ Pinout ATmega329P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 ...
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... Figure 1-2. TQFP / Pinout ATmega3290P 1 LCDCAP 2 (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 3 4 (XCK/AIN0/PCINT2) PE2 5 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 6 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 9 10 VCC 11 GND 12 DNC 13 (PCINT24/SEG35) PJ0 14 (PCINT25/SEG34) PJ1 15 DNC 16 DNC 17 DNC 18 DNC 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 ...
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... PROGRAMMING LOGIC USART DATA REGISTER PORTE The Atmel All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two inde- pendent registers to be accessed in one single instruction executed in one clock cycle. The 8021GS–AVR–03/11 PF0 - PF7 PA0 - PA7 ...
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... C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between ATmega329P, and ATmega3290P. The ATmega329P, and ATmega3290P differ only in pin count and pinout. summarizes the different configurations for the four devices. Table 2-1. Device ATmega329P ATmega3290P 8021GS– ...
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Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...
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... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290P as listed on page 87. ...
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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characteristics” on page 2.3.13 XTAL1 ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...
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... Reserved - (0xCA) Reserved - (0xC9) Reserved - (0xC8) Reserved - (0xC7) UDR0 (0xC6) UBRR0H (0xC5) 8021GS–AVR–03/11 Registers with bold type only available in ATmega3290P. Bit 6 Bit 5 Bit 4 SEG338 SEG337 SEG336 SEG330 SEG329 SEG328 SEG322 SEG321 SEG320 SEG314 SEG313 SEG312 SEG306 SEG305 SEG304 ...
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Address Name Bit 7 UBRR0L (0xC4) Reserved - (0xC3) UCSR0C - (0xC2) UCSR0B RXCIE0 (0xC1) UCSR0A RXC0 (0xC0) Reserved - (0xBF) Reserved - (0xBE) Reserved - (0xBD) Reserved - (0xBC) Reserved - (0xBB) USIDR (0xBA) USISR USISIF (0xB9) USICR USISIE ...
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Address Name Bit 7 TCNT1H (0x85) TCNT1L (0x84) Reserved - (0x83) TCCR1C FOC1A (0x82) TCCR1B ICNC1 (0x81) TCCR1A COM1A1 (0x80) DIDR1 - (0x7F) DIDR0 ADC7D (0x7E) Reserved - (0x7D) ADMUX REFS1 (0x7C) ADCSRB - (0x7B) ADCSRA ADEN (0x7A) ADCH (0x79) ...
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Address Name Bit 7 TCNT0 0x26 (0x46) Reserved - 0x25 (0x45) TCCR0A FOC0A 0x24 (0x44) GTCCR TSM 0x23 (0x43) EEARH - 0x22 (0x42) EEARL 0x21 (0x41) EEDR 0x20 (0x40) EECR - 0x1F (0x3F) GPIOR0 0x1E (0x3E) EIMSK PCIE 0x1D (0x3D) ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...
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Mnemonics Operands PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8021GS–AVR–03/11 Description STACK ← ← STACK (see specific descr. for Sleep ...
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... Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. ...
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... Tape & Reel 5. See Appendix A ATmega169PA/329P/3290P 105°C 100A 100-lead 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 8021GS–AVR–03/11 (2) Ordering Code ATmega3290PV-10AU (4) ATmega3290PV-10AUR ATmega3290P-20AU (4) ATmega3290P-20AUR ATmega3290P-AN 64A (4) ATmega3290P-ANR 64A ATmega3290P-MN 64M1 (4) ATmega3290P-MNR 64M1 and Figure 28-3 on page ...
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Packaging Information 9.1 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...
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Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R ...
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PIN 0°~7° L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...
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Errata 10.1 ATmega329P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer • Using BOD disable will make the chip reset 1. Interrupts may be lost when writing the timer registers in ...
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... Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 10.6 ATmega3290P rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00 ...
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... Updated ”Packaging Information” on page Updated last page. Updated ”Errata” on page 416. Updated the last page with Atmel’s new addresses. ATmega329P/3290P Power-down Supply Current. 349, ”ATmega3290P” on page ”ATmega6490P” on page 473. All other typical chara 410. 413. 30. 373, 24 ...
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... C” on page 416 C” on page 417. Updated.”Errata” on page 416. Updated ”Features” on page 1. Updated ”System and Reset Characteristics” on page Updated ”Typical Characteristics” on page Initial version. ATmega329P/3290P 14. 30. ”External Interrupts” on page 58. 90. 336. and ”ATmega3290P rev. 336. 342. 25 ...
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