DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet
DSPIC30F4011-20E/PT
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... Microchip Technology Inc. dsPIC30F4011/4012 High-Performance, 16-Bit Digital Signal Controllers Data Sheet DS70135G ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle • ±16-bit, single-cycle shift © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F4012 28 48K/16K 2048 dsPIC30F4011 40/44 48K/16K 2048 DS70135G-page 4 CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low-power consumption Output Motor ...
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... PWM3L/RE4 8 33 AN6/OCFA/RB6 PWM3H/RE5 AN7/RB7 AN8/RB8 C1RX/RF0 C1TX/RF1 SS 28 OSC1/CLKI 13 U2RX/CN17/RF4 14 27 U2TX/CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 26 PGD/EMUD/U1TX/SDO1/SCL/RF3 16 25 FLTA/INT0/RE8 17 24 SCK1/RF6 18 23 EMUC2/OC1/IC1/INT1/RD0 OC4/RD3 19 22 OC3/RD2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F4011 AN8/RB8 27 7 AN7/RB7 26 8 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 11 DS70135G-page 5 ...
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... Pin Diagrams (Continued) (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70135G-page dsPIC30F4011 OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 externally. ...
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... AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2010 Microchip Technology Inc. dsPIC30F4011/4012 MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 ...
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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU Architecture Overview........................................................................................................................................................ 17 3.0 Memory Organization ................................................................................................................................................................. 25 4.0 Address Generator Units ............................................................................................................................................................ 37 5.0 Interrupts .................................................................................................................................................................................... 43 6.0 Flash Program Memory .............................................................................................................................................................. 49 7.0 Data EEPROM Memory ............................................................................................................................................................. 55 8.0 I/O Ports ..................................................................................................................................................................................... 61 9.0 Timer1 Module ........................................................................................................................................................................... 67 10.0 Timer2/3 Module ........................................................................................................................................................................ 71 11.0 Timer4/5 Module ....................................................................................................................................................................... 77 12.0 Input Capture Module................................................................................................................................................................. 81 13 ...
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... MCU and DSC Programmer’s Reference (DS70157). This document contains device-specific information for the dsPIC30F4011/4012 devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-2 illustrate device block diagrams for the dsPIC30F4011 and dsPIC30F4012 devices. © ...
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... FIGURE 1-1: dsPIC30F4011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 Control Block PCH PCU Program Counter Loop Stack Address Latch Control Control Logic Logic Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch Instruction Decode and ...
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... Start-up Timer POR/BOR Reset MCLR Watchdog Timer Input Capture CAN 10-bit ADC Module SPI1, Timers QEI SPI2 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 X Data Bus Data Latch Data Latch Y Data X Data RAM RAM 16 (1 Kbyte) (1 Kbyte) Address Address Latch Latch RAGU ...
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... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F4011 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...
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... TABLE 1-1: dsPIC30F4011 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB8 I/O ST RC13-RC15 I/O ST RD0-RD3 I/O ST RE0-RE5, I/O ST RE8 RF0-RF6 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 I ST ...
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... Table 1-2 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... Schmitt Trigger input with CMOS levels I = Input © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. In-Circuit Serial Programming™ data input/output pin. ...
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... NOTES: DS70135G-page 16 © 2010 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 • SWWLinear indirect access of 32K word pages within program space is also possible, using any working register via table read and write instruc- tions ...
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... Programmer’s Model The programmer’s model is shown in consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Coun- ter (PC) ...
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... FIGURE 2-1: dsPIC30F4011/4012 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG 22 DOSTART OAB SAB DA SRH © 2010 Microchip Technology Inc. dsPIC30F4011/4012 D15 D0 W0/WREG W1 W2 ...
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... Divide Support The dsPIC DSCs feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2010 Microchip Technology Inc. dsPIC30F4011/4012 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70135G-page 21 ...
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... MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the mul- tiplier input value ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 2.4.2.2 Accumulator ‘Write-Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... Device ID, the User ID and the Configuration bits; otherwise, bit 23 is always clear. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F4011/4012 Reset – GOTO Instruction Reset – Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’). © 2010 Microchip Technology Inc. dsPIC30F4011/4012 A set of table instructions is provided to move byte or word-sized data to and from program space (see Figure 3-3 and Figure 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Program Space 0x0000 (1) PSVPAG 0x00 8 ...
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... FIGURE 3-6: dsPIC30F4011/4012 DATA SPACE MEMORY MAP MSB Address 0x0001 2-Kbyte SFR Space 0x07FF 0x0801 2-Kbyte 0x0BFF 0x0C01 SRAM Space 0x0FFF 0x1001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70135G-page 30 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2010 Microchip Technology Inc. dsPIC30F4011/4012 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only Indirect EA using W8, W9 ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend uninitialized bit; — = unimplemented ...
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... NOTES: DS70135G-page 36 © 2010 Microchip Technology Inc. ...
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... Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2010 Microchip Technology Inc. dsPIC30F4011/4012 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2010 Microchip Technology Inc. dsPIC30F4011/4012 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister, MODCON<15:0>, contains enable flags as well 3-3 register field to specify the W Address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly ...
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... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 Note 1: Modifier values for buffer sizes greater than 1024 words will exceed the available data memory on the dsPIC30F4011/4012 devices. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Bit-Reversed Address Decimal ...
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... NOTES: DS70135G-page 42 © 2010 Microchip Technology Inc. ...
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... For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157). The dsPIC30F4011/4012 has 30 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the interrupt vector to the program counter ...
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... Interrupt Priority The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx regis- ter(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 5.3 Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error which adhere to a predefined priority, as shown in ...
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... Address Error Trap This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from an unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
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... STATUS registers to return the processor to its state prior to the interrupt sequence. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 5.5 Alternate Interrupt Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2010 Microchip Technology Inc. dsPIC30F4011/4012 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time, and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2010 Microchip Technology Inc. dsPIC30F4011/4012 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70135G-page 54 © 2010 Microchip Technology Inc. ...
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... NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instruc- tions are used to read and write data EEPROM. The dsPIC30F4011/4012 devices have 1 Kbyte (512 words) of data EEPROM, with an address range from 0x7FFC00 to 0x7FFFFE. A word write operation should be preceded by an erase of the corresponding memory location(s) ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70135G-page 60 © 2010 Microchip Technology Inc. ...
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... WR PORT Read LAT Read PORT © 2010 Microchip Technology Inc. dsPIC30F4011/4012 the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...
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... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR PORT Data Latch Read LAT Read PORT 8.2 ...
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... TABLE 8-1: dsPIC30F4011 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...
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TABLE 8-2: dsPIC30F4012 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 ...
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... Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These bits are not available on dsPIC30F4012 devices. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Bit 5 Bit 4 Bit 3 Bit 2 CN4IE CN3IE ...
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... NOTES: DS70135G-page 66 © 2010 Microchip Technology Inc. ...
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... Interrupt on 16-bit Period register match or falling edge of external gate signal © 2010 Microchip Technology Inc. dsPIC30F4011/4012 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit, TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2010 Microchip Technology Inc. dsPIC30F4011/4012 9.5.1 RTC OSCILLATOR OPERATION When TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register, and is then reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE Note: The dsPIC30F4011/4012 devices do not have external pin inputs to Timer3. In these devices, the following modes should not be used: 1. TCS = 1. 2. TCS = 0 and TGATE = 1 (gated time accumulation). © 2010 Microchip Technology Inc. dsPIC30F4011/4012 PR2 TMR2 Q ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70135G-page 76 © 2010 Microchip Technology Inc. ...
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... Timer configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are as follows: • ...
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... TIMER5 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T5IF Event Flag 1 TGATE Note: The dsPIC30F4011/4012 devices do not have an external pin input to Timer5. In these devices, the following modes should not be used: 1. TCS = 1. 2. TCS = 0 and TGATE = 1 (gated time accumulation). DS70135G-page 78 PR4 TMR4 Q D TGATE ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70135G-page 80 © 2010 Microchip Technology Inc. ...
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... Timer2 and Timer3 mode selection • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where ...N). The dsPIC30F4011/4012 devices have four capture channels. Note: The dsPIC30F4011/4012 devices have four capture inputs: IC1, IC2, IC7 and IC8. ...
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... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM< ...
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... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respec- tive Capture Channel Interrupt Enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IECx register. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 DS70135G-page 83 ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC7BUF 0158 IC7CON 015A — — ICSIDL ...
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... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where ... N). The dsPIC30F4011/4012 devices have 4/2 compare channels, respectively. OCxRS and OCxR in the figure represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits, OCM< ...
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... Timer3 is referred to in the figure for clarity. FIGURE 13-1: PWM OUTPUT TIMING Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS © 2010 Microchip Technology Inc. dsPIC30F4011/4012 • OSC Period TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS TMR3 = Duty Cycle (OCxR) ...
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... Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state ...
Page 89
TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — (2) ...
Page 90
... NOTES: DS70135G-page 90 © 2010 Microchip Technology Inc. ...
Page 91
... Programmable INDX Digital Filter 3 Up/Down Note: In dsPIC30F4011/4012, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
Page 92
... Quadrature Encoder Interface Logic A typical, incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...
Page 93
... To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 14.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode, QEIM< ...
Page 94
... QEI Module Operation During CPU Idle Mode Since the QEI module can function as a quadrature encoder interface 16-bit timer, the following section describes operation of the module in both modes. 14.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI mod- ule will operate if the QEISIDL bit (QEICON< ...
Page 95
TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — POSCNT 0126 MAXCNT 0128 ADPCFG 02A8 — — ...
Page 96
... NOTES: DS70135G-page 96 © 2010 Microchip Technology Inc. ...
Page 97
... Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution • ‘On-the-Fly’ PWM frequency changes • ...
Page 98
... FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM Time Base Note: Details of PWM Generators 1 and 2 are not shown for clarity. DS70135G-page 98 PWM Enable and Mode SFRs Dead-Time Control SFRs ...
Page 99
... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
Page 100
... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional func- tions to the user ...
Page 101
... PTMR Value 0 Duty Cycle Period © 2010 Microchip Technology Inc. dsPIC30F4011/4012 15.4 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in a Continuous Up/Down Count mode (see The PWM compare output is driven to the active state ...
Page 102
... PWM Duty Cycle Comparison Units There are three 16-bit Special Function Registers (PDC1, PDC2 and PDC3) used to specify duty cycle values for the PWM module. The value in each duty cycle register determines the amount of time that the PWM output is in the active state ...
Page 103
... DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Dead-Time A (Active) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 DTAPS<1:0> control bits in the DTCON1 SFR. One of four clock prescaler options (T may be selected. After the prescaler value is selected, the dead time is 15-4, each adjusted by loading 6-bit unsigned values into the DTCON1 SFR ...
Page 104
... Independent PWM Output An Independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PTMODx bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent Output mode and both I/O pins are allowed to be active simultaneously ...
Page 105
... The Fault pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 15.12.2 FAULT STATES The FLTACON Special Function Register has six bits that determine the state of each PWM I/O pin when it is overridden by a Fault input ...
Page 106
... PWM Update Lockout For a complex PWM application, the user may need to write up to three duty cycle registers and the Time Base Period register, PTPER given time. In some appli- cations important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module ...
Page 107
TABLE 15-1: 6-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA ...
Page 108
... NOTES: DS70135G-page 108 © 2010 Microchip Technology Inc. ...
Page 109
... SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPI1BUF is read by user software. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Transmit writes are also double-buffered. The user writes to SPI1BUF. When the master or slave transfer is completed, the contents of the shift register (SPI1SR) is moved to the receive buffer ...
Page 110
... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit, FRMEN, enables framed SPI support and causes the SS1 pin to perform the frame synchronization pulse (FSYNC) function. The control bit, SPIFSD, determines whether ...
Page 111
... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 had been deasserted in the middle of a transmit/receive. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down. If ...
Page 112
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend uninitialized bit; ...
Page 113
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 17.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
Page 114
... FIGURE 17-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Start, Restart, Stop bit Generate Acknowledge Shift Clock DS70135G-page 114 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Generation Clock Stretching I2CTRN LSB Reload ...
Page 115
... ACK received from the master. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 116
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 117
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific or a general call address. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 2 17. Master Support As a master device, six operations are supported. ...
Page 118
... I C MASTER RECEPTION Master mode reception is enabled by programming the receive enable (RCEN) bit (I2CCON<3>). The I module must be Idle before the RCEN bit is set, other- wise the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin toggles and data is shifted in to the I2CRSR on the rising edge of each clock ...
Page 119
TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...
Page 120
... NOTES: DS70135G-page 120 © 2010 Microchip Technology Inc. ...
Page 121
... UTXBRK Data UxTX Parity Note dsPIC30F4012 only has UART1. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 18.1 UART Module Overview The key features of the UART module are: • Full-Duplex 9-bit Data Communication • Even, Odd or No Parity Options (for 8-bit data) • One or Two Stop bits • ...
Page 122
... FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70135G-page 122 Internal Data Bus 16 Write Read UxMODE UxRXREG Low Byte URX8 Receive Buffer Control – ...
Page 123
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2010 Microchip Technology Inc. dsPIC30F4011/4012 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 124
... TRANSMIT INTERRUPT The Transmit Interrupt Flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 125
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this special mode in which a 9th bit (URX8) value of ‘ ...
Page 126
... Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit ...
Page 127
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 128
... NOTES: DS70135G-page 128 © 2010 Microchip Technology Inc. ...
Page 129
... CAN modules or digital signal controller devices. This inter- face/protocol was designed to allow communications within noisy environments. The dsPIC30F4011/4012 devices have 1 CAN module. The CAN module is a communication controller imple- menting the CAN 2.0 A/B protocol, as defined in the BOSCH specification ...
Page 130
... FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS (1) (1) TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic C1TX Note 1: These are conceptual groups of registers, not SFR names by themselves. DS70135G-page 130 Acceptance Mask (1) TXB2 (1) RXM0 ...
Page 131
... Disable mode. The I/O pins will revert to normal I/O function when the module is in the Disable mode. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The module can be programmed to apply a low-pass filter function to the C1RX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (C1CFG2< ...
Page 132
... Message Reception 19.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the message assembly buffer (MAB). There are two receive buffers, visibly denoted as RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine ...
Page 133
... TXERR (C1TXxCON<4>) flag automatically cleared. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. If the transmission completes successfully on the first attempt, the TXREQ bit is cleared automatically and an interrupt is generated if TXxIE was set ...
Page 134
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXxIF flags will indicate which transmit buffer is available and caused the interrupt ...
Page 135
... The following requirement must be fulfilled while setting the lengths of the phase segments: Propagation Segment + Phase1 Seg > = Phase2 Seg © 2010 Microchip Technology Inc. dsPIC30F4011/4012 19.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec fixed tive bit ...
Page 136
TABLE 19-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> C1RXF1SID 0308 — — ...
Page 137
TABLE 19-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer 1 Byte 7 C1TX1CON ...
Page 138
... NOTES: DS70135G-page 138 © 2010 Microchip Technology Inc. ...
Page 139
... REF REF feature of being able to operate while the device is in Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • ...
Page 140
... FIGURE 20-1: 10-BIT, HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM REF REF AN0 AN0 AN3 AN6 AN1 AN1 AN4 AN7 AN2 AN2 AN5 AN8 AN0 AN1 AN2 AN3 AN3 AN4 AN4 AN5 AN5 AN6 (1) AN6 AN7 (1) AN7 (1) AN8 AN8 AN1 Note 1: Not available on dsPIC30F4012 devices. ...
Page 141
... The channels are then converted sequentially. Obviously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The CHPS<1:0> bits select how many channels are sampled. This selection can vary from channels. If the CHPS bits select 1 channel, the CH0 channel is sampled at the sample clock and converted ...
Page 142
... Programming the Start of the Conversion Trigger The conversion trigger terminates acquisition and starts the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...
Page 143
... Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See REF REF circuit. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Table 20-1 Max. V Temperature S DD 500Ω 4.5V -40°C to +85°C to 5.5V ANx 500Ω 4.5V -40° ...
Page 144
... The analog input multiplexer must be configured so that the same input pin is connected to both sample and hold channels. The A/D converts the value held on one S&H channel while the second S&H channel acquires a new input sample. DS70135G-page 144 dsPIC30F4011 20.7.1.2 The ADC can also be used to sample multiple analog inputs using multiple sample and hold channels ...
Page 145
... ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 20.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins are to be sampled. ...
Page 146
... A/D Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 20-3. The total sampling time for the ADC is a function of the internal amplifier settling time, device V and the holding capacitor charge time. DD For the ADC to meet its specified accuracy, the charge ...
Page 147
... Integer 0 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 If the A/D interrupt is enabled, the device wakes up from Sleep. If the A/D interrupt is not enabled, the ADC module is then turned off, although the ADON bit remains set ...
Page 148
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the ...
Page 149
TABLE 20-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 150
... NOTES: DS70135G-page 150 © 2010 Microchip Technology Inc. ...
Page 151
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 152
... TABLE 21-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 153
... FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI Internal Fast RC Oscillator (FRC) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock ...
Page 154
... Oscillator Configurations 21.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) The FOS<1:0> Configuration bits that select one of four oscillator groups. b) The FPR<3:0> Configuration bits that select one of 13 oscillator choices within the primary group ...
Page 155
... OSCTUN functionality has been provided to help customers compensate temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 TABLE 21-4: TUN<3:0> Bits 0111 0110 0101 0100 0011 0010 ...
Page 156
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM<1:0> Configuration bits (Clock Switch and Monitor Selection bits) in the F device Configuration register. If the FSCM function is ...
Page 157
... Reset The dsPIC30F4011/4012 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset caused by trap lock-up (TRAPR) h) Reset caused by illegal opcode using an ...
Page 158
... FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL RESET FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL RESET FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 159
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 160
... Table 21-5 lists the Reset conditions for the RCON Register. Since the control bits within the RCON regis- ter are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 21-5: ...
Page 161
... The format of the PWRSAV instruction is as follows: PWRSAV <parameter> where, ‘parameter’ defines Idle or Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 21.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shut down on-chip oscillator is being used shut down. ...
Page 162
... Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level can wake-up the processor. The processor processes the interrupt and branches to the ISR. The SLEEP status bit in the RCON register is set upon wake-up. Note: In spite of various delays applied (T ...
Page 163
... These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 In each case, the selected EMUD pin is the emulation/ debug data line and the EMUC pin is the emulation/ debug clock line. These pins interface to the MPLAB ICD 2 module available from Microchip ...
Page 164
TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST — OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 Legend: — = unimplemented bit, read as ‘0’ Note ...
Page 165
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modi- fier) or file register (specified by the value of ‘ ...
Page 166
... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...
Page 167
... Y Data Space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y Data Space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Description DS70135G-page 167 ...
Page 168
... TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 169
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 # of Description words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 170
... TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 171
... Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2010 Microchip Technology Inc. dsPIC30F4011/4012 # of Description words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 172
... TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd ...
Page 173
... Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2010 Microchip Technology Inc. dsPIC30F4011/4012 23.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 174
... MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
Page 175
... Microchip Technology Inc. dsPIC30F4011/4012 23.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
Page 176
... PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
Page 177
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± ...
Page 178
... DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.5-5.5V -40°C to +85°C 4.5-5.5V -40°C to +125°C 3.0-3.6V -40°C to +85°C 3.0-3.6V -40°C to +125°C 2.5-3.0V -40°C to +85°C TABLE 24-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F401X-30I Operating Junction Temperature Range ...
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... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...
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... TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC31a 2 4 DC31b 2 4 DC31c 2 4 DC31e 3 5 DC31f 3 5 DC31g 3 5 DC30a 4 6 DC30b 4 6 DC30c 4 6 DC30e 7 10 DC30f 7 10 DC30g 7 10 DC23a 12 19 DC23b ...
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... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2010 Microchip Technology Inc. dsPIC30F4011/4012 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
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... TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60a 0.3 — DC60b 1 30 DC60c 12 60 DC60e 0.5 — DC60f 2 45 DC60g 17 90 DC61a 5 8 DC61b 5 8 DC61c 6 9 DC61e 10 15 DC61f 10 15 DC61g 11 17 DC62a ...
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... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 5: Negative current is defined as current sourced by the pin. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
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... TABLE 24-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO ( Osc mode) V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO ( Osc mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...
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... EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ ...
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... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 24-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 24-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
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... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... TABLE 24-14: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
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... CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F © 2010 Microchip Technology Inc. dsPIC30F4011/4012 MIPS MIPS (2) (μsec) (3) w/o PLL w/PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — ...
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... TABLE 24-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Param Characteristic No. Internal FRC Accuracy @ FRC Freq. = 7.37 MHz OS63 FRC Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN<3:0> bits can be used to compensate for temperature drift ...
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... Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 DI35 DI40 New Value DO31 DO32 for load. ...
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... FIGURE 24-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 V DD MCLR Internal POR SY11 PWRT Time-out SY30 Oscillator Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to the Figure 24-2 for load conditions. ...
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... Start-up Time Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
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... FIGURE 24-7: TIMERx EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRx Note: Refer to Figure 24-2 for load conditions. TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H T1CK High Synchronous, TX Time no prescaler Synchronous, with prescaler Asynchronous TA11 T L T1CK Low ...
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... TxCK Low Time TC15 TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, 0 — ...
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... FIGURE 24-8: QEI MODULE EXTERNAL CLOCK TIMING CHARACTERISTICS QEB POSCNT TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ10 TtQH TxCK High Time TQ11 TtQL TxCK Low Time TQ15 TtQP TxCK Input Period Synchronous, TQ20 T Delay from External TxCK Clock ...
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... ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 IC10 IC11 IC15 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40° ...
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... FIGURE 24-10: OUTPUT COMPARE MODULE TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) Note: Refer to TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param (1) Symbol Characteristic No. OC10 TccF OCx Output Fall Time OC11 TccR OCx Output Rise Time Note 1: These parameters are characterized but not tested in manufacturing. ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
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... FIGURE 24-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS FLTA MP20 PWMx FIGURE 24-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS PWMx Note: Refer to Figure 24-2 TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. MP10 T PWM Output Fall Time ...