DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet
DSPIC30F4011-20E/PT
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DSPIC30F4011-20E/PT Summary of contents
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... Rev. A4 Silicon Errata The dsPIC30F4011/4012 (Rev. A4) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70141 – “dsPIC30F3010/3011 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
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... Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 11. INT0, ADC and Sleep Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero ...
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... L1 ;and exit L0:DAW.b w2 L1: .... © 2008 Microchip Technology Inc. dsPIC30F4011/4012 3. Module: Special Function Registers The I/O Port register values can be changed by writing to the following address locations, which are located in unimplemented memory space. A write to these unimplemented addresses could cause an I/O pin configured as an output to change states ...
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... Example 2 is demonstrated in Example 3. DS80398A-page 4 These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F4011/4012 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 6. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported. When device ...
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... Module: Interrupt Controller – Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...
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... Microchip Technology Inc. dsPIC30F4011/4012 10. Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: • The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register ...
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... Module: 10-bit ADC: Sampling Rate The maximum sampling rate for the 10-bit Analog-to-Digital Conversion module is 750 ksps. This rate is only achievable when one A/D pin is being used. Configuring the ADC module to use multiple sample-and-hold circuits (see device data sheet), will not improve the conversion speed of the module ...
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... IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2008 Microchip Technology Inc. dsPIC30F4011/4012 Work around To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. In addition, a global variable could be used to keep track of bit 15, so that when an overflow or underflow condition is present on POSCNT, the variable will toggle bit 15 ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Work around None. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 19. Module: I When the I I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication Start” to all devices on the I a bus collision in a multi-master configuration ...
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... Module: Motor Control PWM – PWM Counter Register If the PTDIR bit is set (when PTMR is counting down), and the CPU execution is halted (after a breakpoint is reached), PTMR will start counting PTDIR was zero. Work around None. 21. Module: I/O Port – Port Pin Multiplexed ...
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... APPENDIX A: REVISION HISTORY Revision A (9/2008) Initial version of this document. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 DS80398A-page 13 ...
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... NOTES: DS80398A-page 14 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...