DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet

IC DSPIC MCU/DSP 48K 44TQFP

DSPIC30F4011-20E/PT

Manufacturer Part Number
DSPIC30F4011-20E/PT
Description
IC DSPIC MCU/DSP 48K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
9-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F401120EPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
Data Sheet
High Performance
Digital Signal Controllers
Preliminary
 2005 Microchip Technology Inc.
DS70135C

Related parts for DSPIC30F4011-20E/PT

DSPIC30F4011-20E/PT Summary of contents

Page 1

... Microchip Technology Inc. dsPIC30F4011/4012 Data Sheet High Performance Digital Signal Controllers Preliminary DS70135C ...

Page 2

... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Enhanced Flash 16-bit Digital Signal Controller Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’ ...

Page 4

... This table provides a summary of the dsPIC30F6010 peripheral features. Other available devices in the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison. ...

Page 5

... PWM3L/RE4 8 33 AN6/OCFA/RB6 PWM3H/RE5 AN7/RB7 AN8/RB8 C1RX/RF0 C1TX/RF1 SS OSC1/CLKIN 13 28 U2RX/CN17/RF4 14 27 U2TX/CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 26 PGD/EMUD/U1TX/SDO1/SCL/RF3 16 25 FLTA/INT0/RE8 17 24 SCK1/RF6 18 23 EMUC2/OC1/IC1/INT1/RD0 OC4/RD3 19 22 OC3/RD2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKIN dsPIC30F4011 AN8/RB8 AN7/RB7 26 8 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 11 Preliminary SS DD DS70135C-page 3 ...

Page 6

... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 CTX1/RF1 CRX1/RF0 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 DS70135C-page dsPIC30F4011 Preliminary OSC2/CLKO/RC15 OSC1/CLKIN AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4  2005 Microchip Technology Inc. ...

Page 7

... Pin Diagrams (Continued) 28-Pin SPDIP 28-Pin SOIC EMUD3/AN0/V REF EMUC3/AN1/V REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC1/CLKIN OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3  2005 Microchip Technology Inc. dsPIC30F4011/4012 MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 PWM1H/RE1 5 24 PWM2L/RE2 PWM2H/RE3 6 23 ...

Page 8

... Table of Contents 1.0 Device Overview ...................................................................................................................................................................... 7 2.0 CPU Architecture Overview.................................................................................................................................................... 15 3.0 Memory Organization ............................................................................................................................................................. 23 4.0 Address Generator Units........................................................................................................................................................ 35 5.0 Interrupts ................................................................................................................................................................................ 41 6.0 Flash Program Memory.......................................................................................................................................................... 47 7.0 Data EEPROM Memory ......................................................................................................................................................... 53 8.0 I/O Ports ................................................................................................................................................................................. 57 9.0 Timer1 Module ....................................................................................................................................................................... 63 10.0 Timer2/3 Module .................................................................................................................................................................... 67 11.0 Timer4/5 Module ................................................................................................................................................................... 73 12.0 Input Capture Module............................................................................................................................................................. 77 13 ...

Page 9

... This document contains device specific information for the dsPIC30F4011/4012 devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for the dsPIC30F4011 and dsPIC30F4012 device. Preliminary device. The dsPIC30F DS70135C-page 7 ...

Page 10

... FIGURE 1-1: dsPIC30F4011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...

Page 11

... Start-up Timer POR/BOR Reset MCLR Watchdog Timer Input 10-bit ADC Capture CAN Module SPI1, Timers QEI SPI2  2005 Microchip Technology Inc. dsPIC30F4011/4012 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (1 Kbyte) (1 Kbyte) Address Address Latch Latch RAGU Y AGU ...

Page 12

... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F4011 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...

Page 13

... TABLE 1-1: dsPIC30F4011 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB8 I/O ST 8RC13-RC15 8I/O 8ST RD0-RD3 I/O ST RE0-RE5, I/O ST RE8 RF0-RF6 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 ...

Page 14

... Table 1-2 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...

Page 15

... Schmitt Trigger input with CMOS levels I = Input  2005 Microchip Technology Inc. dsPIC30F4011/4012 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. In-Circuit Serial Programming data input/output pin. ...

Page 16

... NOTES: DS70135C-page 14 Preliminary  2005 Microchip Technology Inc. ...

Page 17

... Programmer’s Reference Manual (DS70030). This document provides a summary dsPIC30F4011/4012 CPU and peripheral function. For a complete description of this functionality, please refer to the dsPIC30F Family Reference Manual (DS70046). 2.1 Core Overview The core has a 24-bit instruction word. The Program Counter (PC bits wide with the Least Significant (LS) bit always clear (see Section 3 ...

Page 18

... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC) ...

Page 19

... FIGURE 2-1: dsPIC30F4011/4012 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH  2005 Microchip Technology Inc. dsPIC30F4011/4012 D15 D0 W0/WREG W10 W11 ...

Page 20

... Divide Support The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...

Page 21

... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In  2005 Microchip Technology Inc. dsPIC30F4011/4012 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70135C-page 19 ...

Page 22

... MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the mul- tiplier input value ...

Page 23

... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.  2005 Microchip Technology Inc. dsPIC30F4011/4012 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...

Page 24

... Data Space Write Saturation In addition to adder/subtractor saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...

Page 25

... Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear.  2005 Microchip Technology Inc. dsPIC30F4011/4012 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F4011/4012 Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory ...

Page 26

... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...

Page 27

... Program Memory ‘Phantom’ Byte (Read as ‘0’).  2005 Microchip Technology Inc. dsPIC30F4011/4012 A set of Table Instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; ...

Page 28

... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MS BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...

Page 29

... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses.  2005 Microchip Technology Inc. dsPIC30F4011/4012 Program Space 0x0000 (1) PSVPAG 0x00 8 ...

Page 30

... FIGURE 3-6: dsPIC30F4011/4012 DATA SPACE MEMORY MAP MS Byte Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 2 Kbyte 0x0BFF 0x0C01 SRAM Space 0x0FFF 0x1001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70135C-page 28 LS Byte 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...

Page 31

... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W  2005 Microchip Technology Inc. dsPIC30F4011/4012 SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops Read Only Indirect EA using W8, W9 ...

Page 32

... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...

Page 33

... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.  2005 Microchip Technology Inc. dsPIC30F4011/4012 There is a Stack Pointer Limit register (SPLIM) associ- ated with the stack pointer. SPLIM is uninitialized at Reset the case for the stack pointer, SPLIM<0> ...

Page 34

... DS70135C-page 32 Preliminary  2005 Microchip Technology Inc. ...

Page 35

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 33 ...

Page 36

... NOTES: DS70135C-page 34 Preliminary  2005 Microchip Technology Inc. ...

Page 37

... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset  2005 Microchip Technology Inc. dsPIC30F4011/4012 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...

Page 38

... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, Move and Accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...

Page 39

... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words  2005 Microchip Technology Inc. dsPIC30F4011/4012 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...

Page 40

... MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the effective address (EA) calculation associated with any W regis- ter important to realize that the address bound- aries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decre- menting buffers) boundary addresses (not just equal to) ...

Page 41

... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 *Modifier values for buffer sizes greater than 1024 words will exceed the available data memory on the dsPIC30F4011/4012 devices.  2005 Microchip Technology Inc. dsPIC30F4011/4012 Decimal ...

Page 42

... NOTES: DS70135C-page 40 Preliminary  2005 Microchip Technology Inc. ...

Page 43

... Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). The dsPIC30F4011/4012 has 30 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address con- tained in the interrupt vector to the program counter ...

Page 44

... Interrupt Priority The user assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the LS 3- bits of each nibble, within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...

Page 45

... Trap Lockout: Occurrence of multiple Trap conditions simulta- neously will cause a Reset.  2005 Microchip Technology Inc. dsPIC30F4011/4012 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...

Page 46

... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...

Page 47

... The RETFIE (Return from Interrupt) instruction will unstack the program counter and status registers to return the processor to its state prior to the interrupt sequence.  2005 Microchip Technology Inc. dsPIC30F4011/4012 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...

Page 48

... DS70135C-page 46 Preliminary  2005 Microchip Technology Inc. ...

Page 49

... Addressing Using Table Instruction User/Configuration Space Select  2005 Microchip Technology Inc. dsPIC30F4011/4012 6.2 Run Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...

Page 50

... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. ...

Page 51

... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP  2005 Microchip Technology Inc. dsPIC30F4011/4012 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...

Page 52

... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...

Page 53

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 51 ...

Page 54

... NOTES: DS70135C-page 52 Preliminary  2005 Microchip Technology Inc. ...

Page 55

... NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instruc- tions are used to read and write data EEPROM. The dsPIC30F4011/4012 device has 1 Kbyte (512 words) of data EEPROM, with an address range from 0x7FFC00 to 0x7FFFFE. A word write operation should be preceded by an erase of the corresponding memory location(s) ...

Page 56

... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in NVMCON register. ...

Page 57

... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete  2005 Microchip Technology Inc. dsPIC30F4011/4012 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...

Page 58

... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...

Page 59

... WR Port Read LAT Read Port  2005 Microchip Technology Inc. dsPIC30F4011/4012 Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...

Page 60

... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR Port Data Latch Read LAT Read Port 8.2 ...

Page 61

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 59 ...

Page 62

... DS70135C-page 60 Preliminary  2005 Microchip Technology Inc. ...

Page 63

... CN6PUE CN5PUE CNPU2 00C6 — — Legend uninitialized bit *Not available on dsPIC30F4012 Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.  2005 Microchip Technology Inc. dsPIC30F4011/4012 Bit 5 Bit 4 Bit 3 Bit 2 CN4IE CN3IE CN2IE — — — CN18IE* ...

Page 64

... NOTES: DS70135C-page 62 Preliminary  2005 Microchip Technology Inc. ...

Page 65

... Interrupt on 16-bit period register match or falling edge of external gate signal  2005 Microchip Technology Inc. dsPIC30F4011/4012 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...

Page 66

... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...

Page 67

... XTAL SOSCO pF 100K  2005 Microchip Technology Inc. dsPIC30F4011/4012 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then reset to ‘0’. ...

Page 68

... DS70135C-page 66 Preliminary  2005 Microchip Technology Inc. ...

Page 69

... These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs.  2005 Microchip Technology Inc. dsPIC30F4011/4012 For 32-bit timer/counter operation, Timer2 is the LS Word and Timer3 is the MS Word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...

Page 70

... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...

Page 71

... Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE Note: The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER3. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation)  2005 Microchip Technology Inc. dsPIC30F4011/4012 PR2 TMR2 ...

Page 72

... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...

Page 73

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 71 ...

Page 74

... NOTES: DS70135C-page 72 Preliminary  2005 Microchip Technology Inc. ...

Page 75

... Timer Configuration bit T32, T4CON(<3>) must be set to ‘ control bits are respective to the T4CON register. The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices the following modes should not be used: (1) TCS = 1, (2) TCS = 0 and (3) TGATE = 1 (gated time accumulation)  ...

Page 76

... TIMER4 BLOCK DIAGRAM Equal Comparator x 16 Reset 0 T4IF Event Flag 1 TGATE Note: The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) DS70135C-page 74 PR4 TMR4 Q D TGATE ...

Page 77

... Reset 0 T5IF Event Flag 1 TGATE Note: The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation)  2005 Microchip Technology Inc. dsPIC30F4011/4012 PR5 Comparator x 16 ...

Page 78

... DS70135C-page 76 Preliminary  2005 Microchip Technology Inc. ...

Page 79

... Simple Capture Event mode • Timer2 and Timer3 mode selection • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC30F4011/4012 devices have 4 capture channels. Note: measurement. The dsPIC30F4011/4012 devices have four capture inputs: IC1, IC2, IC7 and IC8 ...

Page 80

... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM< ...

Page 81

... If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin.  2005 Microchip Technology Inc. dsPIC30F4011/4012 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt, based upon the selected number of cap- ture events. The selection number is set by control bits ICI< ...

Page 82

... DS70135C-page 80 Preliminary  2005 Microchip Technology Inc. ...

Page 83

... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC30F4011/4012 devices have 4/2 compare channels, respectively. OCxRS and OCxR in the figure represent the Dual Compare registers. In the dual compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...

Page 84

... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers; Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...

Page 85

... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0.  2005 Microchip Technology Inc. dsPIC30F4011/4012 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...

Page 86

... DS70135C-page 84 Preliminary  2005 Microchip Technology Inc. ...

Page 87

... Programmable INDX Digital Filter 3 Up/Down Note: In dsPIC30F4011/4012, the UPDN pin is not available. Up/Down logic bit can still be polled by software.  2005 Microchip Technology Inc. dsPIC30F4011/4012 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...

Page 88

... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...

Page 89

... To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR.  2005 Microchip Technology Inc. dsPIC30F4011/4012 14.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM< ...

Page 90

... QEI Module Operation During CPU Idle Mode Since the QEI module can function as a quadrature encoder interface 16-bit timer, the following section describes operation of the module in both modes. 14.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI module will operate if the QEISIDL bit (QEICON< ...

Page 91

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 89 ...

Page 92

... NOTES: DS70135C-page 90 Preliminary  2005 Microchip Technology Inc. ...

Page 93

... The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution  2005 Microchip Technology Inc. dsPIC30F4011/4012 • ‘On-the-Fly’ PWM frequency changes • Edge and Center Aligned Output modes • Single Pulse Generation mode • ...

Page 94

... FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTCMP PWM time base Note: Details of PWM Generator #1 and #2 not shown for clarity. DS70135C-page 92 PWM Enable and Mode SFRs Dead-Time Control SFRs ...

Page 95

... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR.  2005 Microchip Technology Inc. dsPIC30F4011/4012 15.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...

Page 96

... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional func- tions to the user ...

Page 97

... PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled.  2005 Microchip Technology Inc. dsPIC30F4011/4012 15.5.1 DUTY CYCLE REGISTER BUFFERS The three PWM duty cycle registers are double buff- ered to allow glitchless updates of the PWM outputs. ...

Page 98

... Dead-Time Generators Dead-time generation may be provided when any of the PWM I/O pin pairs are operating in the Comple- mentary Output mode. The PWM outputs use Push- Pull drive circuits. Due to the inability of the power out- put devices to switch instantaneously, some amount of ...

Page 99

... PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated.  2005 Microchip Technology Inc. dsPIC30F4011/4012 15.10 PWM Output Override The PWM output override bits allow the user to manu- ally drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...

Page 100

... PWM Output and Polarity Control There are three device configuration bits associated with the PWM module that provide PWM output pin control: • HPOL configuration bit • LPOL configuration bit • PWMPIN configuration bit These three bits in the FPORBOR configuration regis- ter (see Section 21) work in conjunction with the three PWM Enable bits (PWMEN< ...

Page 101

... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode.  2005 Microchip Technology Inc. dsPIC30F4011/4012 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS< ...

Page 102

... DS70135C-page 100 Preliminary  2005 Microchip Technology Inc. ...

Page 103

... Both the transmit buffer (SPI1TXB) and the receive buffer (SPI1RXB) are mapped to the same register address, SPI1BUF.  2005 Microchip Technology Inc. dsPIC30F4011/4012 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPI1BUF. The interrupt is generated at the middle of the transfer of the last bit ...

Page 104

... FIGURE 16-1: SPI BLOCK DIAGRAM Read SPI1BUF Receive SDI1 bit0 SDO1 SS & FSYNC Control SS1 SCK1 Note: In dsPIC30F4012, the SS1 pin is not available. FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master Serial Input Buffer (SPIxBUF) Shift Register (SPIxSR) MSb PROCESSOR 1 Note ...

Page 105

... MS bit, even if SS1 had been de-asserted in the middle of a transmit/receive. Note that in dsPIC30F4012, the SS1 pin is not available.  2005 Microchip Technology Inc. dsPIC30F4011/4012 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down. If ...

Page 106

... DS70135C-page 104 Preliminary  2005 Microchip Technology Inc. ...

Page 107

... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15  2005 Microchip Technology Inc. dsPIC30F4011/4012 17.1.1 VARIOUS I The following types • Slave operation with 7-bit address 2 • Slave operation with 10-bit address 2 • ...

Page 108

... FIGURE 17- BLOCK DIAGRAM Shift SCL Clock SDA Stop bit Detect Stop bit Generate Shift Clock DS70135C-page 106 I2CRCV I2CRSR LSB Addr_Match Match Detect I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down ...

Page 109

... ACK received from the master.  2005 Microchip Technology Inc. dsPIC30F4011/4012 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...

Page 110

... MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 17.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching ...

Page 111

... When the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific general call address.  2005 Microchip Technology Inc. dsPIC30F4011/4012 2 17. Master Support As a Master device, six operations are supported. ...

Page 112

... I C MASTER RECEPTION Master mode reception is enabled by programming the receive enable (RCEN) bit (I2CCON<11>). The I module must be Idle before the RCEN bit is set, other- wise the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin toggles, and data is shifted in to the I2CRSR on the rising edge of each clock ...

Page 113

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 111 ...

Page 114

... NOTES: DS70135C-page 112 Preliminary  2005 Microchip Technology Inc. ...

Page 115

... Data UxTX Parity Note dsPIC30F4012 only has UART1.  2005 Microchip Technology Inc. dsPIC30F4011/4012 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • ...

Page 116

... FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70135C-page 114 Internal Data Bus 16 Read Write UxRXREG Low Byte URX8 Receive Buffer Control – ...

Page 117

... The STSEL bit determines whether one or two stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 stop bit (typically represented 1).  2005 Microchip Technology Inc. dsPIC30F4011/4012 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA MODE ...

Page 118

... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR) ...

Page 119

... No further reception can occur until a stop bit is received. Note that RIDLE goes high when the stop bit has not been received yet.  2005 Microchip Technology Inc. dsPIC30F4011/4012 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this special mode, in which a 9th bit (URX8) value of ‘ ...

Page 120

... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the start bit ...

Page 121

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 119 ...

Page 122

... NOTES: DS70135C-page 120 Preliminary  2005 Microchip Technology Inc. ...

Page 123

... The Controller Area Network (CAN) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices. This interface/ protocol was designed to allow communications within noisy environments. The dsPIC30F4011/4012 have 1 CAN module. The CAN module is a communication controller imple- menting the CAN 2.0 A/B protocol, as defined in the BOSCH specification ...

Page 124

... FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic C1TX DS70135C-page 122 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 c e Acceptance Filter p RXF1 t R Identifier Data Field ...

Page 125

... The I/O pins will revert to normal I/O function when the module is in the module disable mode.  2005 Microchip Technology Inc. dsPIC30F4011/4012 The module can be programmed to apply a low-pass filter function to the C1RX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (C1CFG2< ...

Page 126

... Message Reception 19.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the message assembly buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can ...

Page 127

... TXERR (C1TXnCON<4>) flag automatically cleared.  2005 Microchip Technology Inc. dsPIC30F4011/4012 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. If the transmission completes successfully on the first attempt, the TXREQ bit is cleared automatically and an interrupt is generated if TXIE was set ...

Page 128

... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt ...

Page 129

... The following requirement must be fulfilled while setting the lengths of the Phase Segments: • Propagation Segment + Phase1 Seg > = Phase2 Seg  2005 Microchip Technology Inc. dsPIC30F4011/4012 19.6.5 SAMPLE POINT The Sample Point is the point of time at which the bus level is read and interpreted as the value of that respec- ...

Page 130

... DS70135C-page 128 Preliminary  2005 Microchip Technology Inc. ...

Page 131

... Microchip Technology Inc. dsPIC30F4011/4012 Preliminary DS70135C-page 129 ...

Page 132

... NOTES: DS70135C-page 130 Preliminary  2005 Microchip Technology Inc. ...

Page 133

... The A/D converter has a unique feature of being able to operate while the device is in Sleep mode.  2005 Microchip Technology Inc. dsPIC30F4011/4012 The A/D module has six 16-bit registers: • A/D Control Register1 (ADCON1) • A/D Control Register2 (ADCON2) • ...

Page 134

... FIGURE 20-1: 10-BIT HIGH SPEED A/D FUNCTIONAL BLOCK DIAGRAM REF V + REF V - AN0 AN0 AN3 AN6 AN1 AN1 AN4 AN7 AN2 AN2 AN5 AN8 AN0 AN1 AN2 AN3 AN3 AN4 AN4 AN5 AN5 AN6 *AN6 AN7 *AN7 AN8 *AN8 AN1 * = Not available on dsPIC30F4012. ...

Page 135

... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable.  2005 Microchip Technology Inc. dsPIC30F4011/4012 The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...

Page 136

... Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...

Page 137

... DAC) Note: C PIN value depends on device package and is not tested. Effect of C  2005 Microchip Technology Inc. dsPIC30F4011/4012 The user must allow at least 1 T SAMP time between conversions to allow each sam- ple to be acquired. This sample time may be controlled ...

Page 138

... Module Power-down Modes The module has 3 internal power modes. When the ADON bit is ‘1’, the module is in Active mode fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings ...

Page 139

... ANx pins), may cause the input buffer to consume current that exceeds the device specifications.  2005 Microchip Technology Inc. dsPIC30F4011/4012 20.13 Connection Considerations The analog inputs have diodes to V protection. This requires that the analog input be between V ...

Page 140

... DS70135C-page 138 Preliminary  2005 Microchip Technology Inc. ...

Page 141

... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power.  2005 Microchip Technology Inc. dsPIC30F4011/4012 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...

Page 142

... TABLE 21-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/ PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/ PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/ PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...

Page 143

... FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI Internal Fast RC Oscillator (FRC)  2005 Microchip Technology Inc. dsPIC30F4011/4012 PLL F PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock ...

Page 144

... Oscillator Configurations 21.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> configuration bits that select one of four oscillator groups. b) AND FPR<3:0> configuration bits that select one of 13 oscillator choices within the primary group ...

Page 145

... FRC oscillator frequency to be adjusted as close to 8 MHz as possible, depending on the device operating conditions. The FRC oscillator frequency has been calibrated during factory testing. Table 21-4 describes the adjustment range of the TUN<3:0> bits.  2005 Microchip Technology Inc. dsPIC30F4011/4012 TABLE 21-4: TUN<3:0> Bits 0111 0110 ...

Page 146

... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM configuration bits (Clock Switch and Monitor Selection bits) in the F configuration register. If the FSCM function is enabled, ...

Page 147

... Reset The dsPIC30F4011/4012 differentiates between vari- ous kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset cause by trap lockup (TRAPR) h) Reset caused by illegal opcode using an ...

Page 148

... FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...

Page 149

... The BOR voltage trip points indicated here are nominal values provided for design guidance only.  2005 Microchip Technology Inc. dsPIC30F4011/4012 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device configuration bit values (FOS<1:0> and FPR< ...

Page 150

... Table 21-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON regis- ter are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 21-5: ...

Page 151

... These are: Sleep and Idle. The format of the PWRSAV instruction is as follows: PWRSAV <parameter>, where ‘parameter’ defines Idle or Sleep mode.  2005 Microchip Technology Inc. dsPIC30F4011/4012 21.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shutdown on-chip oscillator is being used shutdown ...

Page 152

... Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. The Sleep status bit in RCON register is set upon wake-up. ...

Page 153

... These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and MUD3/EMUC3.  2005 Microchip Technology Inc. dsPIC30F4011/4012 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line. These pins will interface to the MPLAB ICD 2 module available from Microchip ...

Page 154

... DS70135C-page 152 Preliminary  2005 Microchip Technology Inc. ...

Page 155

... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’  2005 Microchip Technology Inc. dsPIC30F4011/4012 Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modi- fier) or file register (specified by the value of ‘ ...

Page 156

... Most single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...

Page 157

... Y data space pre-fetch address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Wyd  2005 Microchip Technology Inc. dsPIC30F4011/4012 Description Preliminary DS70135C-page 155 ...

Page 158

... TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...

Page 159

... Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd  2005 Microchip Technology Inc. dsPIC30F4011/4012 Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> ...

Page 160

... TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DISI DISI #lit14 30 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 31 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 34 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 35 EXCH EXCH Wns,Wnd 36 FBCL FBCL Ws,Wnd 37 FF1L FF1L ...

Page 161

... Ws,Wnd 70 SETM SETM f SETM WREG SETM Ws  2005 Microchip Technology Inc. dsPIC30F4011/4012 Description Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * ...

Page 162

... TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 71 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 73 SUB SUB Acc SUB f SUB f,WREG SUB #lit10,Wn SUB Wb,Ws,Wd SUB Wb,#lit5,Wd 74 SUBB SUBB f SUBB f,WREG SUBB ...

Page 163

... CAN ® - PowerSmart - Analog  2005 Microchip Technology Inc. dsPIC30F4011/4012 23.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 164

... MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...

Page 165

... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2005 Microchip Technology Inc. dsPIC30F4011/4012 23.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...

Page 166

... PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...

Page 167

... Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.  2005 Microchip Technology Inc. dsPIC30F4011/4012 23.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

Page 168

... NOTES: DS70135C-page 166 Preliminary  2005 Microchip Technology Inc. ...

Page 169

... Temp Range 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C  2005 Microchip Technology Inc. dsPIC30F4011/4012 DD (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V DD ) ..........................................................................................................± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latchup. ...

Page 170

... TABLE 24-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F401x-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F401x-20I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F401x-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation × ...

Page 171

... All I/O pins are configured as Inputs and pulled MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating.  2005 Microchip Technology Inc. dsPIC30F4011/4012 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...

Page 172

... TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC27 — — DC27a 52 — DC27b — — DC27c — — DC27d 94 — DC27e — — DC27f — — DC28 — — DC28a 41 — DC28b — — ...

Page 173

... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. IDLE 2: Base I current is measured with Core off, Clock on and all modules turned off.  2005 Microchip Technology Inc. dsPIC30F4011/4012 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...

Page 174

... TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. IDLE Idle Current (I ): Core OFF Clock ON Base Current DC47 — — DC47a 33 — DC47b — — DC47c — — DC47d 56 — DC47e — — DC47f — — DC48 — — ...

Page 175

... LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should added to the base I current.  2005 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial A Operating temperature -40° ...

Page 176

... TABLE 24-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No Input Low Voltage DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL IH V Input High Voltage ...

Page 177

... These parameters are characterized but not tested in manufacturing. FIGURE 24-1: BROWN-OUT RESET CHARACTERISTICS DD V BO10 (Device in Brown-out Reset) RESET (due to BOR)  2005 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...

Page 178

... TABLE 24-10: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. (2) BOR BO10 V BOR Voltage DD V transition high to low BHYS BO15 V Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. ...

Page 179

... Load Condition 1 - for all pins except OSC2 Pin FIGURE 24-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT  2005 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ Operating voltage V range as described in DC Spec Section 24.0. ...

Page 180

... TABLE 24-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OSC OS10 F External CLKIN Frequency (External clocks allowed only in EC mode) Oscillator Frequency OSC OSC OSC OS20 1/F OS25 T CY Instruction Cycle Time (2) OS30 TosL, External Clock in (OSC1) TosH High or Low Time ...

Page 181

... Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle].  2005 Microchip Technology Inc. dsPIC30F4011/4012 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ Operating temperature -40°C ≤ (1) (2) Min Typ Max ...

Page 182

... TABLE 24-16: AC CHARACTERISTICS: INTERNAL RC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Param Characteristic No. Internal FRC Accuracy @ FRC Freq = 7.37 MHz FRC FRC with x4 PLL FRC with x8 PLL FRC with x16 PLL Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. ...

Page 183

... Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 24-18: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq = 512 kHz F20 F21 Note 1: Frequency at 25°C and 5V.  2005 Microchip Technology Inc. dsPIC30F4011/4012 -40°C ≤ -40°C ≤ Min Typ Max Units (1) TBD % TBD % -40° ...

Page 184

... FIGURE 24-4: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 24-2 for load conditions. TABLE 24-19: CLKOUT AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 Port output rise time IO DO32 T F Port output fall time ...

Page 185

... DD V SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-2 for load conditions.  2005 Microchip Technology Inc. dsPIC30F4011/4012 SY10 SY20 SY13 Preliminary SY13 DS70135C-page 183 ...

Page 186

... TABLE 24-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) PWRT SY11 T Power-up Timer Period SY12 T POR Power On Reset Delay IOZ SY13 T I/O Hi-impedance from MCLR ...

Page 187

... TCS (T1CON, bit 1)) CKEXTMRL TA20 T Delay from External TxCK Clock Edge to Timer Increment  2005 Microchip Technology Inc. dsPIC30F4011/4012 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...

Page 188

... TABLE 24-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, CKEXTMRL TB20 T Delay from External TxCK Clock Edge to Timer Increment TABLE 24-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS ...

Page 189

... CKEXTMRL TQ20 T Delay from External TxCK Clock Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing.  2005 Microchip Technology Inc. dsPIC30F4011/4012 TQ10 TQ11 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...

Page 190

... FIGURE 24-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS X IC Note: Refer to Figure 24-2 for load conditions. TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...

Page 191

... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2005 Microchip Technology Inc. dsPIC30F4011/4012 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...

Page 192

... FIGURE 24-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS FLTA/B MP20 PWMx FIGURE 24-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS PWMx Note: Refer to Figure 24-2 for load conditions. TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...

Page 193

... Note 1: These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” in the dsPIC30F Family Reference Manual.  2005 Microchip Technology Inc. dsPIC30F4011/4012 TQ36 TQ30 TQ31 TQ35 TQ41 TQ40 ...

Page 194

... FIGURE 24-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ51 Index Internal Position TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ50 TqIL Filter Time to Recognize Low, with Digital Filter TQ51 TqiH ...

Page 195

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins.  2005 Microchip Technology Inc. dsPIC30F4011/4012 SP10 SP21 SP20 BIT14 - - - - - -1 MSb SP30 BIT14 - - - -1 Standard Operating Conditions: 2 ...

Page 196

... FIGURE 24-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 X SCK (CKP = 0) SP11 X SCK (CKP = 1) X MSb SDO SP40 SP30,SP31 X SDI MSb IN SP41 Note: Refer to Figure 24-2 for load conditions. TABLE 24-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS ...

Page 197

... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins.  2005 Microchip Technology Inc. dsPIC30F4011/4012 SP70 SP73 SP72 MSb BIT14 - - - - - -1 SP30,SP31 ...

Page 198

... FIGURE 24-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 X SS SP50 SCK X (CKP = 0) SP71 X SCK (CKP = 1) MSb X SDO X SDI SDI MSb IN SP41 SP40 Note: Refer to Figure 24-2 for load conditions. DS70135C-page 196 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb ...

Page 199

... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins.  2005 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...

Page 200

... FIGURE 24-20 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 24-2 for load conditions. 2 FIGURE 24-21 BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 24-2 for load conditions. ...

Related keywords