DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 113

IC DSPIC MCU/DSP 48K 44TQFP

DSPIC30F4011-20E/PT

Manufacturer Part Number
DSPIC30F4011-20E/PT
Description
IC DSPIC MCU/DSP 48K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
9-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F401120EPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial Clock Synchronization for I
• I
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
FIGURE 17-1:
© 2010 Microchip Technology Inc.
Note:
Operation
ing
addressing
Master and Slaves
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
collision and will arbitrate accordingly
2
2
2
2
2
C Interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit address-
C Master mode supports 7-bit and 10-bit
C Port allows Bidirectional Transfers between
C supports Multi-Master Operation; detects bus
I
Operating Function Description
2
2
C™ MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
C module can operate either as a slave or
2
C bus.
2
C Standard and Fast mode
PROGRAMMER’S MODEL
bit 15
bit 15
2
C serial communication
2
C™) module provides
2
C Port can be
bit 9
bit 8
bit 7
bit 7
17.1.1
The following types of I
• I
• I
• I
See the I
17.1.2
I
SDA pin is data.
17.1.3
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read-only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written or from which data bytes are read.
I2CRCV is the receive buffer, as shown in
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and
transmission, the I2CTRN is not double-buffered.
2
C has a 2-pin interface. The SCL pin is clock and the
Note:
2
2
2
dsPIC30F4011/4012
C slave operation with 7-bit addressing
C slave operation with 10-bit addressing
C master operation with 7-bit or 10-bit addressing
an
17-2.
2
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
C programmer’s model in
interrupt
VARIOUS I
PIN CONFIGURATION IN I
I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
C REGISTERS
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16-bits)
I2CSTAT (16-bits)
I2CADD (10-bits)
pulse
2
C operation are supported:
2
C MODES
is
generated.
DS70135G-page 113
Figure
Figure
2
17-1.
C MODE
During
17-1.

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