DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 159

• Manufacturer Part Number: DSPIC30F4011-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401120EPT

21.3.1.1
The oscillator start-up circuitry is not linked to the POR
circuitry. Some
frequency crystals) have a relatively long start-up time.
Therefore, one or more of the following conditions is
possible after the POR timer and the PWRT have
expired:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap occurs. The device
automatically switches to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
21.3.1.2
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device exits rapidly
from Reset on power-up. If the clock source is FRC,
LPRC, ERC or EC, it will be active immediately.
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s
perspective, the device will appear to be in Reset until
a system clock is available.
21.3.2
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines, or voltage sags due to exces-
sive current draw when a large inductive load is turned
on).
The BOR module allows selection of one of the
following voltage trip points (see
• 2.6V-2.71V
• 4.1V-4.4V
• 4.58V-4.73V
© 2010 Microchip Technology Inc.
crystal oscillator is used).
Note:
BOR: PROGRAMMABLE
BROWN-OUT RESET
The BOR voltage trip points indicated here
are nominal values provided for design
guidance only.
POR with Long Crystal Start-up Time
(with FSCM Enabled)
Operating without FSCM and PWRT
crystal circuits (especially low-
Table
24-10):
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FOS<1:0> and
FPR<3:0>). Furthermore, if an oscillator mode is
selected, the BOR activates the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock is held until
the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the POR time-out (T
time-out (T
is released. If T
being used, then a nominal delay of T
applied. The total delay in this case is (T
The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit, if enabled, contin-
ues to operate while in Sleep or Idle modes and resets
the device if V
FIGURE 21-6:
Note:
Note 1: External Power-on Reset circuit is required
dsPIC30F4011/4012
2: R should be suitably chosen so as to make
3: R1 should be suitably chosen so as to limit
PWRT
D
Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
only if the V
The diode D helps discharge the capacitor
quickly when V
sure that the voltage drop across R does not
violate the device’s electrical specification.
any current flowing into MCLR from external
capacitor C, in the event of MCLR pin break-
down, due to Electrostatic Discharge (ESD)
or Electrical Overstress (EOS).
DD
V
) are applied before the internal Reset
PWRT
falls below the BOR threshold voltage.
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
= 0 and a crystal oscillator is
DD
DD
R1
power-up slope is too slow.
powers down.
DD
MCLR
dsPIC30F
POR
DS70135G-page 159
POWER-UP)
FSCM
) and the PWRT
POR
= 100 μs is
+ T
FSCM
).