DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 162

• Manufacturer Part Number: DSPIC30F4011-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401120EPT

dsPIC30F4011/4012
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level can wake-up the processor. The processor
processes the interrupt and branches to the ISR. The
SLEEP status bit in the RCON register is set upon
wake-up.
All Resets wake-up the processor from Sleep mode.
Any Reset, other than POR, sets the SLEEP status bit.
In a POR, the SLEEP bit is cleared.
If Watchdog Timer is enabled, the processor wakes-up
from Sleep mode upon WDT time-out. The SLEEP and
WDTO status bits are both set.
21.5.2
In Idle mode, the clock to the CPU is shut down while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module,
that allows them to operate during Idle.
LPRC Fail-Safe Clock Monitor remains active if clock
failure detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• Any interrupt that is individually enabled (IE bit is
• Any Reset (POR, BOR, MCLR)
• WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins
immediately, starting with the instruction following the
PWRSAV instruction.
DS70135G-page 162
Note:
‘1’) and meets the required priority level
In spite of various delays applied (T
T
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency crys-
tals). In such cases, if FSCM is enabled,
the device detects this condition as a
clock failure and processes the clock fail-
ure trap. The FRC oscillator is enabled,
and the user must re-enable the crystal
oscillator. If FSCM is not enabled, then the
device simply suspends execution of code
until the clock is stable and remains in
Sleep until the oscillator clock has started.
IDLE MODE
LOCK
and T
PWRT
), the crystal oscillator
POR
,
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level can wake-up the
processor. The processor processes the interrupt and
branches to the ISR. The IDLE status bit in RCON
register is set upon wake-up.
Any Reset, other than POR, sets the IDLE status bit.
On a POR, the IDLE bit is cleared.
If Watchdog Timer is enabled, then the processor
wakes-up from Idle mode upon WDT time-out. The
IDLE and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
21.6
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming™ (ICSP™) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are five device
Configuration registers available to the user:
1.
2.
3.
4.
5.
The placement of the Configuration bits is automatically
handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For additional
information,
specifications of the device.
Note:
FOSC (0xF80000): Oscillator Configuration
Register
FWDT (0xF80002): Watchdog Timer
Configuration Register
FBORPOR (0xF80004): BOR and POR
Configuration Register
FGS (0xF8000A): General Code Segment
Configuration Register
FICD (0xF8000C): Debug Configuration
Register
Device Configuration Registers
If the code protection Configuration fuse
bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages V
please
refer
© 2010 Microchip Technology Inc.
to
DD
the
≥ 4.5V.
programming