AT89C5131A-PUTUM Atmel, AT89C5131A-PUTUM Datasheet - Page 126

IC 8051 MCU FLASH 32K USB 32QFN

AT89C5131A-PUTUM

Manufacturer Part Number
AT89C5131A-PUTUM
Description
IC 8051 MCU FLASH 32K USB 32QFN
Manufacturer
Atmel
Series
AT89C513xr
Datasheet

Specifications of AT89C5131A-PUTUM

Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Core
8051
Processor Series
AT89x
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Data Ram Size
1.25 KB
Number Of Programmable I/os
34
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
Height
0.95 mm
Interface Type
2-Wire, EUART, SPI, USB
Length
7 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7 mm
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C5131A-PUTUM
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
21.4.1
126
AT89C5130A/31A-M
Bulk/Interrupt OUT Transactions in Standard Mode
Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode
An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB con-
troller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If
the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register val-
ues are equal to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0 bit to
allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0 bit
has been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct and the
endpoint byte counter contains the number of bytes sent by the Host.
OUT
OUT
OUT
OUT
HOST
DATA0 (n bytes)
DATA1
DATA1
DATA1
ACK
NAK
NAK
ACK
UFI
RXOUTB0
RXOUTB0
Endpoint FIFO read byte 1
Endpoint FIFO read byte 2
Endpoint FIFO read byte n
Endpoint FIFO read byte 1
Clear RXOUTB0
C51
4337K–USB–04/08

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