ATMEGA324A-PU Atmel, ATMEGA324A-PU Datasheet - Page 176

IC MCU AVR 32K 20MHZ 40PDIP

ATMEGA324A-PU

Manufacturer Part Number
ATMEGA324A-PU
Description
IC MCU AVR 32K 20MHZ 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA324A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
Atmega
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
18.4.4
18.5
8272A–AVR–01/10
Frame Formats
Synchronous Clock Operation
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 18-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As
be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data
will be changed at falling XCKn edge and sampled at rising XCKn edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 18-4 on page 177
brackets are optional.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
UCPOL = 1
UCPOL = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
RxD / TxD
RxD / TxD
XCK
XCK
illustrates the possible combinations of the frame formats. Bits inside
Figure 18-3 on page 176
f
XCK
<
f
---------- -
OSC
4
shows, when UCPOLn is zero the data will
Sample
Sample
176

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