ATMEGA324A-PU Atmel, ATMEGA324A-PU Datasheet - Page 577

• Manufacturer Part Number: ATMEGA324A-PU
• Description: IC MCU AVR 32K 20MHZ 40PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: Atmega
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8272A–AVR–01/10
21 AC - Analog Comparator ..................................................................... 238
22 ADC - Analog-to-digital Converter ..................................................... 241
23 JTAG Interface and On-chip Debug System ..................................... 261
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 267
164A/164PA/324A/324PA/644A/644PA/1284/1284P
20.22-wire Serial Interface Bus Definition ..................................................................208
20.3Data Transfer and Frame Format ........................................................................209
20.4Multi-master Bus Systems, Arbitration and Synchronization ...............................212
20.5Overview of the TWI Module ...............................................................................214
20.6Using the TWI ......................................................................................................216
20.7Transmission Modes ...........................................................................................219
20.8Multi-master Systems and Arbitration ..................................................................232
20.9Register Description ............................................................................................233
21.1Overview .............................................................................................................238
21.2Analog Comparator Multiplexed Input .................................................................238
21.3Register Description ............................................................................................239
22.1Features ..............................................................................................................241
22.2Overview .............................................................................................................241
22.3Operation .............................................................................................................242
22.4Starting a Conversion ..........................................................................................243
22.5Prescaling and Conversion Timing ......................................................................244
22.6Changing Channel or Reference Selection .........................................................247
22.7ADC Noise Canceler ...........................................................................................249
22.8ADC Conversion Result ......................................................................................254
22.9Register Description ............................................................................................256
23.1Features ..............................................................................................................261
23.2Overview .............................................................................................................261
23.3TAP – Test Access Port ......................................................................................261
23.4TAP Controller .....................................................................................................263
23.5Using the Boundary-scan Chain ..........................................................................264
23.6Using the On-chip Debug System .......................................................................264
23.7On-chip Debug Specific JTAG Instructions .........................................................265
23.8Using the JTAG Programming Capabilities .........................................................265
23.9Bibliography .........................................................................................................266
23.10Register Description ..........................................................................................266
24.1Features ..............................................................................................................267
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