ATMEGA324A-PU Atmel, ATMEGA324A-PU Datasheet - Page 66

IC MCU AVR 32K 20MHZ 40PDIP

ATMEGA324A-PU

Manufacturer Part Number
ATMEGA324A-PU
Description
IC MCU AVR 32K 20MHZ 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA324A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
Atmega
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.3
11.3.1
8272A–AVR–01/10
Register Description
MCUCR – MCU Control Register
Note:
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section
details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must
be followed to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See the following Code Example.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
0x35 (0x55)
Read/Write
Initial Value
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
1. Only available in the ATmega164PA/324PA/644PA/1284P.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
for details on Boot Lock bits.
JTD
R/W
7
0
BODS
6
R
0
(1)
BODSE
R
5
0
(1)
PUD
R/W
4
0
”Memory Programming” on page 295
R
3
0
”Memory Programming” on page 295
R
2
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
for
66

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