ATMEGA324A-PU Atmel, ATMEGA324A-PU Datasheet - Page 74

IC MCU AVR 32K 20MHZ 40PDIP

ATMEGA324A-PU

Manufacturer Part Number
ATMEGA324A-PU
Description
IC MCU AVR 32K 20MHZ 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA324A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
Atmega
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
13.2
13.2.1
8272A–AVR–01/10
Ports as General Digital I/O
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 13-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
92, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
SLEEP
(1)
SYNCHRONIZER
D
L
Q
Q
D
PINxn
Q
Q
RESET
RESET
PORTxn
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
PUD
WDx
RDx
RPx
clk
1
0
Figure 13-2
I/O
WRx
WPx
shows a func-
”Register
I/O
,
74

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