DSPIC33FJ64GS608-E/PT Microchip Technology, DSPIC33FJ64GS608-E/PT Datasheet

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DSPIC33FJ64GS608-E/PT

Manufacturer Part Number
DSPIC33FJ64GS608-E/PT
Description
MCU/DSP 16BIT 64KB FLASH 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ64GS608-E/PT

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
74
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
74
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 18 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Price
Part Number:
DSPIC33FJ64GS608-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ64GS608-E/PT
Manufacturer:
MIC
Quantity:
20 000
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
Preliminary
 2010 Microchip Technology Inc.
DS70591C

Related parts for DSPIC33FJ64GS608-E/PT

DSPIC33FJ64GS608-E/PT Summary of contents

Page 1

... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70591C ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA  2010 Microchip Technology Inc. dsPIC33FJ64GS406/606/608/610 Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • Output pins can drive voltage from 3.0V to 3.6V • ...

Page 4

... Dedicated result buffer for each analog channel • Independent trigger source section for each analog input conversion pairs Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep, and Doze modes with fast wake-up Preliminary  2010 Microchip Technology Inc. ...

Page 5

... Watchdog Timer with its RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources • In-Circuit Serial Programming™ (ICSP™) • Reference Oscillator Output  2010 Microchip Technology Inc. Application Examples: • AC-to-DC Converters • Automotive HID • Battery Chargers • ...

Page 6

... Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CONTROLLER FAMILIES Device dsPIC33FJ32GS406 dsPIC33FJ32GS606 dsPIC33FJ32GS608 dsPIC33FJ32GS610 100 dsPIC33FJ64GS406 (1) dsPIC33FJ64GS606 (1) dsPIC33FJ64GS608 (1) dsPIC33FJ64GS610 100 Note 1: RAM size is inclusive of 1 Kbyte DMA RAM. DS70591C-page 6x2 6x2 ...

Page 7

... Pin Diagrams 64-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 SCK2/FLT12/CN8/RG6 4 SDI2/FLT11/CN9/RG7 5 SDO2/FLT10/CN10/RG8 6 MCLR 7 SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/AQEB1/CN7/RB5 11 AN4/AQEA1/CN6/RB4 12 AN3/AINDX1/CN5/RB3 13 AN2/ASS1/CN4/RB2 14 PGEC3/B/AN1/CN3/RB1 15 PGED3/AN0/CN2/RB0 16  2010 Microchip Technology Inc. = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 dsPIC33FJ32GS406 dsPIC33FJ64GS406 40 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 ...

Page 8

... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS70591C-page dsPIC33FJ32GS406 9 dsPIC33FJ64GS406 Preliminary = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 32  2010 Microchip Technology Inc. ...

Page 9

... Pin Diagrams (Continued) 64-Pin TQFP PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0  2010 Microchip Technology Inc dsPIC33FJ32GS606 Preliminary = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 ...

Page 10

... TQFP PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 DS70591C-page dsPIC33FJ64GS606 Preliminary = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3  2010 Microchip Technology Inc. ...

Page 11

... QFN PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS  2010 Microchip Technology Inc dsPIC33FJ32GS606 Preliminary ...

Page 12

... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS70591C-page dsPIC33FJ64GS606 Preliminary = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 48 PGED2/SOSCI/T4CK/CN1/RC13 47 OC1/QEB1/FLT5/RD0 46 IC4/QEA1/FLT4/INT4/RD11 45 IC3/INDX1/FLT3/INT3/RD10 44 IC2/FLT2/U1CTS/INT2/RD9 43 IC1/FLT1/SYNCI1/INT1/RD8 OSC2/REFCLKO/CLKO/RC15 40 OSC1/CLKIN/RC12 SCL1/RG2 37 SDA1/RG3 36 U1RTS/SCK1/INT0/RF6 35 U1RX/SDI1/RF2 34 U1TX/SDO1/RF3 33 32  2010 Microchip Technology Inc. ...

Page 13

... PWM4L/RE6 2 PWM4H/RE7 3 AN16/T2CK/RC1 4 AN17/T3CK/RC2 5 SCK2/FLT12/CN8/RG6 6 SDI2/FLT11/CN9/RG7 7 SDO2/FLT10/CN10/RG8 8 MCLR 9 SS2/FLT9/T5CK/CN11/RG9 TMS/FLT13/INT1/RE8 13 TDO/FLT14/INT2/RE9 14 AN5/CMP3B/AQEB1/CN7/RB5 15 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 16 AN3/CMP2B/AINDX1/CN5/RB3 17 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 18 PGEC3/AN1/CMP1B/CN3/RB1 19 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 20  2010 Microchip Technology Inc. = Pins are tolerant dsPIC33FJ32GS608 Preliminary PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/SYNCI1/RD8 SDA2/INT4/FLT19/RA15 SCL2/INT3/FLT20/RA14 V SS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 ...

Page 14

... MCLR 9 SS2/FLT9/T5CK/CN11/RG9 TMS/FLT13/INT1/RE8 13 TDO/FLT14/INT2/RE9 14 AN5/CMP3B/AQEB1/CN7/RB5 15 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 16 AN3/CMP2B/AINDX1/CN5/RB3 17 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 18 PGEC3/AN1/CMP1B/CN3/RB1 19 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 20 DS70591C-page 14 = Pins are tolerant dsPIC33FJ64GS608 Preliminary  2010 Microchip Technology Inc. PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/SYNCI1/RD8 SDA2/INT4/FLT19/RA15 SCL2/INT3/FLT20/RA14 V SS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 ...

Page 15

... AN16/T2CK/RC1 6 AN17/T3CK/RC2 7 AN18/T4CK/RC3 8 AN19/T5CK/RC4 9 SCK2/FLT12/CN8/RG6 10 SDI2/FLT11/CN9/RG7 11 SDO2/FLT10/CN10/RG8 12 MCLR 13 SS2/FLT9/CN11/RG9 TMS/RA0 17 AN20/FLT13/INT1/RE8 18 AN21/FLT14/INT2/RE9 19 AN5/CMP3B/AQEB1/CN7/RB5 20 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 21 AN3/CMP2B/AINDX1/CN5/RB3 22 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 23 PGEC3/AN1/CMP1B/CN3/RB1 24 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 25  2010 Microchip Technology Inc. = Pins are tolerant dsPIC33FJ32GS610 Preliminary Vss PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/RD8 INT4/FLT19/SYNCI4/RA15 INT3/FLT20/RA14 V SS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 ...

Page 16

... AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 21 AN3/CMP2B/AINDX1/CN5/RB3 22 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 23 PGEC3/AN1/CMP1B/CN3/RB1 24 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 25 DS70591C-page 16 = Pins are tolerant dsPIC33FJ64GS610 Preliminary  2010 Microchip Technology Inc. Vss PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/RD8 INT4/FLT19/SYNCI4/RA15 INT3/FLT20/RA14 V SS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 V DD TDO/RA5 TDI/RA4 SDA2/FLT21/RA3 SCL2/FLT22/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 ...

Page 17

... Appendix A: Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Devices ................................................................................................................................ 403 Appendix B: Revision History............................................................................................................................................................. 404 Index ................................................................................................................................................................................................. 409 The Microchip Web Site ..................................................................................................................................................................... 415 Customer Change Notification Service .............................................................................................................................................. 415 Customer Support .............................................................................................................................................................................. 415 Reader Response .............................................................................................................................................................................. 416 Product Identification System ............................................................................................................................................................ 417  2010 Microchip Technology Inc. Preliminary DS70591C-page 17 ...

Page 18

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70591C-page 18 Preliminary  2010 Microchip Technology Inc. ...

Page 19

... Digital Signal Controller (DSC) devices: • dsPIC33FJ32GS406 • dsPIC33FJ32GS606 • dsPIC33FJ32GS608 • dsPIC33FJ32GS610 • dsPIC33FJ64GS406 • dsPIC33FJ64GS606 • dsPIC33FJ64GS608 • dsPIC33FJ64GS610 The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 families of devices contain extensive Digital Signal Processor (DSP) func- tionality with a high-performance 16-bit microcontroller (MCU) architecture. ...

Page 20

... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR ECAN1 ADC1 OC1-4 QEI1,2 CNx I2C1,2 Preliminary PORTA DMA RAM 16 PORTB DMA Controller 16 16 PORTC PORTD 16 PORTE 16 PORTF 16 PORTG 16 PWM SPI1,2  2010 Microchip Technology Inc. ...

Page 21

... T5CK I Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic  2010 Microchip Technology Inc. Description Analog input channels External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

Page 22

... Comparator 4 Channel A Comparator 4 Channel B Comparator 4 Channel C Comparator 4 Channel D — DAC output voltage External Voltage Reference Input for the Reference DACs — REFCLK output signal is a postscaled derivative of the system clock Analog = Analog input P = Power Preliminary I = Input O = Output  2010 Microchip Technology Inc. ...

Page 23

... DDCORE Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic  2010 Microchip Technology Inc. Description ST Fault Inputs to PWM Module ST External synchronization signal to PWM Master Time Base — PWM Master Time Base for external device synchronization — ...

Page 24

... NOTES: DS70591C-page 24 Preliminary  2010 Microchip Technology Inc. ...

Page 25

... Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”)  2010 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required ...

Page 26

... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL  2010 Microchip Technology Inc. ...

Page 27

... REAL ICE™ In-Circuit Debugger User's Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749  2010 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...

Page 28

... Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 through Figure 2-11. Preliminary  2010 Microchip Technology Inc ...

Page 29

... FIGURE 2-4: DIGITAL PFC ADC Channel FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION ADC Channel  2010 Microchip Technology Inc. I PFC | FET k 2 Driver ADC Channel PWM Output dsPIC33FJ32GS406 I PFC INPUT FET k 2 Driver ADC PWM Channel Output dsPIC33FJ32GS406 Preliminary ...

Page 30

... Input FET k 7 Driver ADC Channel dsPIC33FJ32GS608 DS70591C-page 30 5V Output I 5V FET Driver Analog ADC Comp. Channel dsPIC33FJ32GS606 FET Driver PWM FET Driver PWM Analog Comparator Analog Comparator Analog Comparator ADC Channel Preliminary 2 3.3V Output  2010 Microchip Technology Inc. ...

Page 31

... OFF-LINE UPS Push-Pull Converter V BAT GND FET FET k Driver Driver 2 PWM PWM ADC or Analog Comp ADC ADC k 6 Battery Charger  2010 Microchip Technology Inc GND FET FET FET FET k Driver Driver Driver Driver 1 ADC PWM PWM PWM PWM ADC dsPIC33FJ64GS610 ADC ...

Page 32

... FIGURE 2-9: INTERLEAVED PFC | ADC Channel ADC Channel DS70591C-page FET FET Driver Driver ADC ADC ADC PWM PWM Channel Channel Channel dsPIC33FJ32GS608 Preliminary V + OUT OUT  2010 Microchip Technology Inc. ...

Page 33

... FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER Gate 3 Gate 1 S1 Gate Gate 1 FET Driver S1 Gate 2  2010 Microchip Technology Inc. Gate 6 S3 Gate 4 Gate 5 Analog Ground PWM Gate 3 FET Driver PWM S3 Gate 4 Preliminary V + OUT V - OUT Gate 5 FET k 2 Driver k 1 ADC ...

Page 34

FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V) ZVT with Current Doubler Synchronous Rectifier V _ Isolation HV BUS Barrier I ZVT FET FET Driver Driver k 4 ADC ADC Channel Channel PWM Primary ...

Page 35

... Microchip Technology Inc. cycle result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. ...

Page 36

... Data Latch Data Latch PCH PCL X RAM Y RAM Address Loop Address Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary and 16-Bit ALU 16 To Peripheral Modules  2010 Microchip Technology Inc. ...

Page 37

... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH  2010 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 ...

Page 38

... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. DS70591C-page 38 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) (1,4) Preliminary R/C R/W-0 (1,4) SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0  2010 Microchip Technology Inc. ...

Page 39

... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB.  2010 Microchip Technology Inc. (2) Preliminary DS70591C-page 39 ...

Page 40

... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70591C-page 40 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set  2010 Microchip Technology Inc. ...

Page 41

... Microchip Technology Inc. 3.5.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit and ...

Page 42

... DS70591C-page 42 Algebraic Operation – y – y change – – 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Preliminary ACC Write Back Yes No No Yes No Yes Yes Round u Logic Zero Backfill  2010 Microchip Technology Inc. ...

Page 43

... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation.  2010 Microchip Technology Inc. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • ...

Page 44

... Section 3.6.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write- back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary to data saturation (see  2010 Microchip Technology Inc. ...

Page 45

... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.  2010 Microchip Technology Inc. 3.6.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

Page 46

... NOTES: DS70591C-page 46 Preliminary  2010 Microchip Technology Inc. ...

Page 47

... Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Reserved  2010 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.6 “ ...

Page 48

... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary and and PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006  2010 Microchip Technology Inc. ...

Page 49

... Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2010 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so and care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

Page 50

... Optionally Mapped into Program Memory 0xFFFF DS70591C-page 50 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 Y Data RAM (Y) 0x17FE 0x1800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 6 Kbyte Near Data Space  2010 Microchip Technology Inc. ...

Page 51

... Kbyte SFR Space 0x07FF 0x0801 0x17FF 0x1801 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF  2010 Microchip Technology Inc. LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 ...

Page 52

... Memory 0xFFFF DS70591C-page 52 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 0x27FE 0x2800 DMA RAM 0x2BFE 0x2C00 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space  2010 Microchip Technology Inc. ...

Page 53

... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device.  2010 Microchip Technology Inc. 4.2.6 DMA RAM Some devices contain 1 Kbyte of dual ported DMA RAM, which is located at the end of Y data space ...

Page 54

TABLE 4-1: CPU CORE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

Page 55

TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...

Page 56

... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES File SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 — — — — 0062 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 — ...

Page 57

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES File SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF ADIF U1TXIF ...

Page 58

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED) File SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> ...

Page 59

... TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF ADIF U1TXIF IFS1 0086 U2TXIF U2RXIF ...

Page 60

... TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC20 00CC — — — — IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — ...

Page 61

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF ADIF U1TXIF ...

Page 62

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC20 00CC — — — — IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 ...

Page 63

TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ...

Page 64

TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC27 00DA ...

Page 65

TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF ...

Page 66

TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> ...

Page 67

TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF IFS1 ...

Page 68

TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> IPC26 ...

Page 69

TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF ...

Page 70

TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> ...

Page 71

TABLE 4-11: TIMERS REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON TON — TSIDL — 0104 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON TON — ...

Page 72

TABLE 4-13: OUTPUT COMPARE REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

Page 73

TABLE 4-16: HIGH-SPEED PWM REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PTCON 0400 PTEN — PTSIDL SESTAT PTCON2 0402 — — — PTPER 0404 SEVTCMP 0406 MDC 040A STCON 040E — — — ...

Page 74

TABLE 4-18: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON2 0442 PENH PENL POLH POLL FCLCON2 0444 IFLTMOD CLSRC<4:0> PDC2 0446 PHASE2 0448 ...

Page 75

TABLE 4-19: HIGH-SPEED PWM GENERATOR 3 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON3 0462 PENH PENL POLH POLL FCLCON3 0464 IFLTMOD CLSRC<4:0> PDC3 0466 PHASE3 0468 ...

Page 76

TABLE 4-20: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON4 0482 PENH PENL POLH POLL FCLCON4 0484 IFLTMOD CLSRC<4:0> PDC4 0486 PHASE4 0488 ...

Page 77

TABLE 4-21: HIGH-SPEED PWM GENERATOR 5 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON5 04A0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON5 04A2 PENH PENL POLH POLL FCLCON5 04A4 IFLTMOD CLSRC<4:0> PDC5 04A6 PHASE5 04A8 ...

Page 78

TABLE 4-22: HIGH-SPEED PWM GENERATOR 6 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON6 04C0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON6 04C2 PENH PENL POLH POLL FCLCON6 04C4 IFLTMOD CLSRC<4:0> PDC6 04C6 PHASE6 04C8 ...

Page 79

TABLE 4-23: HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON7 04E0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON7 04E2 PENH PENL POLH POLL FCLCON7 04E4 IFLTMOD ...

Page 80

TABLE 4-24: HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON8 0500 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON8 0502 PENH PENL POLH POLL FCLCON8 0504 IFLTMOD ...

Page 81

TABLE 4-25: HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON9 0520 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON9 0522 PENH PENL POLH POLL FCLCON9 0524 IFLTMOD ...

Page 82

TABLE 4-27: I2C2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C2RCV 0210 — — — — I2C2TRN 0212 — — — — I2C2BRG 0214 — — — — I2C2CON 0216 I2CEN — I2CSIDL ...

Page 83

TABLE 4-30: SPI1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK DISSDO SPI1CON2 0244 FRMEN SPIFSD FRMPOL — SPI1BUF 0248 Legend: x ...

Page 84

TABLE 4-32: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCON 0300 ADON — ADSIDL SLOWCLK ADPCFG 0302 PCFG15 PCFG14 PCFG13 PCFG12 ADPCFG2 0304 — ...

Page 85

TABLE 4-32: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCBUF22 036C ADCBUF23 036E ADCBUF24 0370 ADCBUF25 0372 Legend unknown value on ...

Page 86

... TABLE 4-33: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCON 0300 ADON — ADSIDL SLOWCLK ADPCFG 0302 PCFG15 PCFG14 PCFG13 PCFG12 ADPCFG2 0304 — — — — ADSTAT 0306 — ...

Page 87

TABLE 4-34: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCON 0300 ADON — ADSIDL SLOWCLK ADPCFG 0302 PCFG15 PCFG14 PCFG13 PCFG12 ADSTAT 0306 — — ...

Page 88

TABLE 4-35: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

Page 89

TABLE 4-36: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0600 — — CSIDL ABAT C1CTRL2 0602 — — — C1VEC 0604 — — — C1FCTRL 0606 ...

Page 90

TABLE 4-38: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0600- 061E C1BUFPNT1 0620 F3BP<3:0> C1BUFPNT2 0622 F7BP<3:0> C1BUFPNT3 0624 F11BP<3:0> C1BUFPNT4 0626 F15BP<3:0> C1RXM0SID 0630 SID<10:3> C1RXM0EID 0632 EID<15:8> ...

Page 91

TABLE 4-38: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11EID 066E EID<15:8> C1RXF12SID 0670 SID<10:3> C1RXF12EID 0672 EID<15:8> C1RXF13SID 0674 SID<10:3> C1RXF13EID 0676 EID<15:8> C1RXF14SID 0678 SID<10:3> C1RXF14EID ...

Page 92

... ODCA 02C6 ODCA15 ODCA14 — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-41: PORTA REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISA 02C0 TRISA15 TRISA14 — ...

Page 93

... RC12 LATC 02D4 LATC15 LATC14 LATC13 LATC12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-44: PORTC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISC 02D0 ...

Page 94

... ODCD 02DE — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-48: PORTE REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISE 02E0 — ...

Page 95

... LATF12 ODCF 02EE — — ODCF13 ODCF12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-51: PORTF REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISF 02E8 — ...

Page 96

... TABLE 4-54: PORTG REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISG 02F0 — — — — PORTG 02F2 — — — — LATG 02F4 — — — — ODCG 02F6 — — — ...

Page 97

TABLE 4-57: NVM REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Name NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...

Page 98

... TABLE 4-60: PMD REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr PMD1 0770 T5MD T4MD T3MD T2MD PMD2 0772 — — — — PMD3 0774 — — — — PMD4 0776 — — — — PMD6 ...

Page 99

TABLE 4-63: PMD REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr PMD1 0770 T5MD T4MD T3MD T2MD PMD2 0772 — — — — PMD3 0774 — — — — PMD4 0776 ...

Page 100

... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary  2010 Microchip Technology Inc. addressing modes are ...

Page 101

... Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes.  2010 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...

Page 102

... W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary space Modulo Addressing EA between the  2010 Microchip Technology Inc. ...

Page 103

... Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment  2010 Microchip Technology Inc. If the length of a bit-reversed buffer the last ‘N’ bits of the data buffer start address must be zeros. ...

Page 104

... TABLE 4-66: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70591C-page 104 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal  2010 Microchip Technology Inc. ...

Page 105

... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>.  2010 Microchip Technology Inc. 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...

Page 106

... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70591C-page 106 Program Counter 0 23 bits TBLPAG 1/0 8 bits 24 bits Select 1 PSVPAG 0 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select  2010 Microchip Technology Inc. ...

Page 107

... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG  2010 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...

Page 108

... PSV Area 0x800000 Preliminary 1111’ or 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address.  2010 Microchip Technology Inc. ...

Page 109

... Using 1/0 Table Instruction User/Configuration Space Select  2010 Microchip Technology Inc. and three other lines for power (V Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed ...

Page 110

... Operations” for further details. Preliminary stalls (waits) until the PROGRAMMING TIME T %   % FRC Accuracy FRC Tuning 11064 Cycles =       0. – 11064 Cycles =       1 0.05 – –  2010 Microchip Technology Inc. ...

Page 111

... No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented.  2010 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...

Page 112

... NVMKEY<7:0>: Key Register bits (write-only) DS70591C-page 112 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...

Page 113

... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP  2010 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...

Page 114

... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary  2010 Microchip Technology Inc. ...

Page 115

... V DD Trap Conflict Illegal Opcode Uninitialized W Register  2010 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure 6-1. Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected ...

Page 116

... DS70591C-page 116 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 117

... OST 10 MHz crystal and for a 32 kHz crystal. OST PLL lock time (1.5 ms nominal) if PLL is enabled. LOCK  2010 Microchip Technology Inc. 2. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset and until V DD delay, T BOR ensures that the voltage regulator output becomes stable ...

Page 118

... The delay, T BOR BOR , ensures that the system power supplies have stabilized at the PWRT has elapsed and the SYSRST becomes PWRT , has elapsed. the Reset Preliminary LOCK OST 6 T FSCM 5 Run crosses DD , ensures the voltage regulator output  2010 Microchip Technology Inc. ...

Page 119

... DD SYSRST V DD SYSRST V dips before PWRT expires SYSRST  2010 Microchip Technology Inc. V threshold and the delay, T BOR delay ensures the voltage regulator output BOR becomes stable. The BOR Status (BOR) bit in the Reset Control , POR (RCON<1>) register is set to indicate the Brown-out Reset ...

Page 120

... Section 24.4 The VFC occurs when the program counter is reloaded with an interrupt or trap vector. Refer to Section 24.8 “Code Protection and CodeGuard™ Security” for more information on Security Reset. Preliminary  2010 Microchip Technology Inc. ...

Page 121

... IDLE (RCON<2>) PWRSAV #IDLE instruction BOR (RCON<1>) POR, BOR POR (RCON<0>) POR Note: All Reset flag bits can be set or cleared by user software.  2010 Microchip Technology Inc. Table 6-2 provides a summary of the Reset flag bit operation. Set by: POR,BOR POR,BOR POR POR,BOR ...

Page 122

... NOTES: DS70591C-page 122 Preliminary  2010 Microchip Technology Inc. ...

Page 123

... The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).  2010 Microchip Technology Inc. Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority ...

Page 124

... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70591C-page 124 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1)  2010 Microchip Technology Inc. ...

Page 125

... Microchip Technology Inc. AIVT Address Highest Natural Order Priority 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...

Page 126

... ADC Pair 2 Convert Done 0x0001F6 ADC Pair 3 Convert Done 0x0001F8 ADC Pair 4 Convert Done 0x0001FA ADC Pair 5 Convert Done 0x0001FC ADC Pair 6 Convert Done 0x0001FE ADC Pair 7 Convert Done Lowest Natural Order Priority Preliminary Interrupt Source  2010 Microchip Technology Inc. ...

Page 127

... IPCx The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.  2010 Microchip Technology Inc. 7.3.5 INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt ...

Page 128

... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set  2010 Microchip Technology Inc. ...

Page 129

... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred  2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

Page 130

... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70591C-page 130 Preliminary  2010 Microchip Technology Inc. ...

Page 131

... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

Page 132

... DS70591C-page 132 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA0IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 133

... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. Preliminary DS70591C-page 133 ...

Page 134

... DS70591C-page 134 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF AC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IF DMA2IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 135

... Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Interrupts disabled on devices without ECAN™ modules  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 136

... DS70591C-page 136 U-0 U-0 R/W-0 — — QEI1IF U-0 U-0 R/W-0 — — MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 U-0 PSEMIF — bit 8 R/W-0 U-0 SI2C2IF — bit Bit is unknown ...

Page 137

... U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts disabled on devices without ECAN™ modules.  2010 Microchip Technology Inc. U-0 R/W-0 U-0 — QEI2IF — ...

Page 138

... DS70591C-page 138 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 ADCP11IF ADCP10IF ADCP9IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 ADCP8IF — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 139

... PWM4IF: PWM4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 PWM3IF: PWM3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 140

... DS70591C-page 140 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 ADCP6IF ADCP5IF ADCP4IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ADCP3IF ADCP2IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 141

... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...

Page 142

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70591C-page 142 Preliminary  2010 Microchip Technology Inc. ...

Page 143

... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 ...

Page 144

... U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 145

... MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEI1IE U-0 U-0 R/W-0 — ...

Page 146

... DS70591C-page 146 U-0 R/W-0 U-0 — QEI2IE — U-0 U-0 R/W-0 — — U2EIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary  2010 Microchip Technology Inc. R/W-0 U-0 PSESMIE — bit 8 R/W-0 U-0 U1EIE — bit Bit is unknown ...

Page 147

... Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 ADCP8IE: ADC Pair 8 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 ...

Page 148

... DS70591C-page 148 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 PWM7IE PWM6IE PWM5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 AC4IE AC3IE bit 8 R/W-0 R/W-0 PWM4IE PWM3IE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 149

... ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 150

... Interrupt is priority 1 000 = Interrupt source is disabled DS70591C-page 150 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 151

... Interrupt source is disabled bit 3-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 152

... Interrupt is priority 1 000 = Interrupt source is disabled DS70591C-page 152 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 153

... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

Page 154

... Interrupt is priority 1 000 = Interrupt source is disabled DS70591C-page 154 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 AC1IP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 155

... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...

Page 156

... Interrupt is priority 1 000 = Interrupt source is disabled DS70591C-page 156 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 157

... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

Page 158

... Note 1: Interrupts disabled on devices without ECAN™ modules DS70591C-page 158 R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown (1)  2010 Microchip Technology Inc. ...

Page 159

... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

Page 160

... Unimplemented: Read as ‘0’ DS70591C-page 160 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MI2C2IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 161

... INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...

Page 162

... Unimplemented: Read as ‘0’ DS70591C-page 162 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 QEI1IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 163

... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...

Page 164

... Note 1: Interrupts disabled on devices without ECAN™ modules DS70591C-page 164 U-0 U-0 R/W-1 — — C1TXIP<2:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 (1) bit 8 U-0 U-0 — — bit Bit is unknown ...

Page 165

... PSESMIP<2:0>: PWM Special Event Secondary Match Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. R/W-0 U-0 U-0 — — R/W-0 U-0 U-0 — ...

Page 166

... Unimplemented: Read as ‘0’ DS70591C-page 166 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 ADCP9IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 167

... Unimplemented: Read as ‘0’ bit 2-0 ADCP11IP<2:0>: ADC Pair 11 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...

Page 168

... Unimplemented: Read as ‘0’ DS70591C-page 168 R/W-0 U-0 R/W-1 — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PWM1IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 169

... Unimplemented: Read as ‘0’ bit 2-0 PWM3IP<2:0>: PWM3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

Page 170

... Interrupt is priority 1 000 = Interrupt source is disabled DS70591C-page 170 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PWM9IP<2:0> bit 8 R/W-0 R/W-0 PWM7IP<2:0> bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 171

... Unimplemented: Read as ‘0’ bit 2-0 AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...

Page 172

... Unimplemented: Read as ‘0’ DS70591C-page 172 R/W-0 U-0 R/W-1 — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 ADCP0IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 173

... Unimplemented: Read as ‘0’ bit 2-0 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 174

... Interrupt source is disabled DS70591C-page 174 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ADCP6IP<2:0> bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 175

... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is number 135 • • • 0000001 = Interrupt vector pending is number 9 0000000 = Interrupt vector pending is number 8  2010 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...

Page 176

... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary  2010 Microchip Technology Inc. ...

Page 177

... UART2RX – UART2 Receiver UART2TX – UART2 Transmitter ECAN1 – RX Data Ready ECAN1 – TX Data Request  2010 Microchip Technology Inc. Direct Memory Access (DMA very efficient mechanism of copying data between peripheral SFRs (e.g., the UART Receive register and Input Capture 1 buffer) and buffers or variables stored in RAM, with minimal CPU intervention ...

Page 178

... An additional pair of STATUS registers, DMACS0 and DMACS1, are common to all DMAC channels. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus Preliminary DMA Ready Peripheral 3 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1  2010 Microchip Technology Inc. ...

Page 179

... MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled  2010 Microchip Technology Inc. R/W-0 R/W-0 U-0 HALF NULLW — ...

Page 180

... See Table 8-1 for a complete listing of IRQ numbers for all interrupt sources. DS70591C-page 180 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 (2) IRQSEL<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 181

... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)  2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ...

Page 182

... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 183

... XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected  2010 Microchip Technology Inc. U-0 R/C-0 R/C-0 — PWCOL3 PWCOL2 U-0 ...

Page 184

... DMA0STA register selected DS70591C-page 184 U-0 R-1 R-1 — LSTCH<3:0> U-0 R-0 R-0 — PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown ...

Page 185

... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits  2010 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...

Page 186

... NOTES: DS70591C-page 186 Preliminary  2010 Microchip Technology Inc. ...

Page 187

... Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.  2010 Microchip Technology Inc. The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 oscillator system provides: • External and internal oscillator options as clock sources • ...

Page 188

... PLL VCO ( ADC and Auxiliary Clock Generator FRCDIVN S7 FRCDIV<2:0> FRCDIV16 S6 FRC S0 LPRC S5 ) SOSC S4 Clock Switch Clock Fail S7 NOSC<2:0> FNOSC<2:0> (3) VCO (1) F SELACLK ENAPLL Preliminary DOZE<2:0> ÷ OSC Reset WDT, PWRT, FSCM Timer 1 ACLK To PWM/ADC ÷ N APSTSCLR<2:0>  2010 Microchip Technology Inc. ...

Page 189

... The LPRC internal oscIllator runs at a nominal frequency of 32.768 kHz also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).  2010 Microchip Technology Inc. The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip and ...

Page 190

... CY 2 Preliminary Note 1, 2 111 1 110 1 101 — 100 — 011 — 011 1 011 — 010 — 010 1 010 1 001 1 000 ’, IN ’ is given by Equation 9-2. F CALCULATION OSC N1*N2 XT WITH PLL MODE EXAMPLE 1 10000000 * MIPS  2010 Microchip Technology Inc. ...

Page 191

... The reference clock output logic provides the user with the ability to output a clock signal based on the system clock or the crystal oscillator on a device pin. The user application can specify a wide range of clock scaling prior to outputting the reference clock.  2010 Microchip Technology Inc. 0.8-8.0 MHz 100-200 MHz (1) Here ...

Page 192

... PLL modes. DS70591C-page 192 (1) R-y U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary  2010 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 U-0 R/W-0 — OSWEN bit Bit is unknown ...

Page 193

... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.  2010 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...

Page 194

... DS70591C-page 194 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 195

... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested.  2010 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 196

... U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) provides the source clock for auxiliary clock divider Preliminary R/W-1 R/W-1 APSTSCLR<2:0> bit 0 U-0 U-0 U-0 — — — Bit is unknown  2010 Microchip Technology Inc. ...

Page 197

... Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock bit 7-0 Unimplemented: Read as ‘0’ Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.  2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ROSEL RODIV<3:0> ...

Page 198

... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. Preliminary (OSCCON<5>) and the CF  2010 Microchip Technology Inc. ...

Page 199

... Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2010 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices have two spe- cial power-saving modes that are entered through the execution of a special PWRSAV instruction ...

Page 200

... When the HRPDIS bit is set, the smallest unit of measure for the PWM period is 8.32 ns. If the HRDDIS bit is set, the smallest unit of measure for the PWM duty cycle, phase offset and dead time is 8.32 ns. Preliminary There are eight possible  2010 Microchip Technology Inc. ...

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