PIC24HJ64GP510-E/PT Microchip Technology, PIC24HJ64GP510-E/PT Datasheet - Page 4

• Manufacturer Part Number: PIC24HJ64GP510-E/PT
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510-E/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC24H ENGINEERING SAMPLES
7. Module: ADC with Timer as Conversion
8. Module: UART Auto-Baud
9. Module: Oscillator: Doze Mode
DS80260B-page 4
The ADC module can be configured so that Timer3
ends ADC sampling and starts the conversion
(ADCON<7:5> = 010). PR3, the Timer3 period
register, is loaded with a value that is compared to
TMR3. In the ADC mode described, when TMR3 is
equal to PR3, an A/D conversion is initiated.
Timer3 can also initiate an A/D conversion when
Timer2 and Timer3 are configured as a single 32-
bit timer. However, when Timer2 and Timer3 are
configured as a single 32-bit timer, an A/D conver-
sion may not be initiated if the PR3 register is set
to ‘0’.
Work around
When Timer3 is selected as the trigger for initiating
an A/D conversion (i.e. ADCON<7:5> = 010),
make sure that PR3 is non-zero.
When auto-baud is enabled (UxMODE<5> is set),
the UART FIFO will be loaded with incorrect data
unless the UxBRG register is initialized to 0xFFFF.
Work around
Initialize the UxBRG register to 0xFFFF anytime
auto-baud is enabled.
Enabling Doze mode slows down the CPU but
allows peripherals to run at full speed. When the
CPU clock is slowed down by enabling Doze mode
(CLKDIV<11> = 1), any writes to a peripheral SFR
can cause other updates to that register to cease
to function for the duration of the current CPU
clock cycle. This is only an issue if the CPU
attempts to write to the same register as a
peripheral while in Doze mode.
For instance, if the ADC module is active and Doze
mode is enabled, the main program should avoid
writing to ADCCONx registers because these reg-
isters are being used by the ADC module. If the
CPU does make writes before the ADC module
does, then any attempts by the ADC module to
write to these registers will fail.
Work around
In Doze mode, avoid writing code that will modify
SFRs which may be written to by enabled
peripherals.
Trigger Source
10. Module: 12-bit ADC
11. Module: 10-bit ADC
1. When the ADC module is configured for 12-bit
2. The conversion speed is limited to 400 Ksps
Work around
Implement the ADC module as either a 10 or 11-bit
A/D Converter.
1. When used as a 10-bit ADC, the INL is <±2
2. When used as an 11-bit ADC, the INL is <±2
Future versions of the silicon will support full 12-bit
operation with <±2 LSBs INL and <±1 LSB DNL, a
500 Ksps conversion rate and a 133 nS signal
acquisition time.
The ADC module INL is >±2 LSBs and DNL is >±1
LSB.
Work around
None. Future versions of the silicon will support
<±2 LSBs INL and <±1 LSB DNL specifications,
and a 70 nS signal acquisition time.
operation, the ADC INL is >±2 LSBs and DNL
is >±1 LSB.
and requires a minimum signal acquisition time
of 266 nS.
LSBs, and DNL is <±1 LSB with no missing
codes.
LSBs and DNL is ±1 LSB with missing codes at
each 2
still realized if the missing codes are ignored.
7
power boundary. ADC monotonicity is
© 2006 Microchip Technology Inc.