ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 219

• Manufacturer Part Number: ATMEGA32U4-MU
• Description: MCU AVR 32K FLASH 16MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Interface Type: EBI/I2S/SPI/TWI/USART/USB
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 5
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA32U4-16MU; ATMEGA32U4-16MU

19.5.1
19.5.2
19.6
19.6.1
19.6.2
7766F–AVR–11/10
USART MSPIM Register Description
Transmitter and Receiver Flags and Interrupts
Disabling the Transmitter or Receiver
USART MSPIM I/O Data Register - UDRn
USART MSPIM Control and Status Register n A - UCSRnA
Note:
The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode
are identical in function to the normal USART operation. However, the receiver error status flags
(FE, DOR, and PE) are not in use and is always read as zero.
The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to
the normal USART operation.
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
normal USART operation. See “USART I/O Data Register n– UDRn” on page 205.
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
Bit
Read/Write
Initial Value
1. See “Code Examples” on page 8.
7
RXCn
R/W
0
6
TXCn
R/W
0
5
UDREn
R/W
0
4
-
R
0
3
-
R
0
2
-
R
1
1
-
R
1
ATmega16/32U4
0
-
R
0
UCSRnA
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