ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 281

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ATMEGA32U4-MU

Manufacturer Part Number
ATMEGA32U4-MU
Description
MCU AVR 32K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA32U4-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Interface Type
EBI/I2S/SPI/TWI/USART/USB
On-chip Adc
12-chx10-bit
Number Of Timers
5
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16MU
ATMEGA32U4-16MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
22.18.2
7766F–AVR–11/10
USB device endpoint registers
• Frame Number Lower Value
Set by hardware. These bits are the 8 LSB of the 11-bits Frame Number information.
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - FNCERR -Frame Number CRC Error Flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
• 3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - EPNUM2:0 Endpoint Number Bits
Load by software to select the number of the endpoint which shall be accessed by the CPU. See
Section 22.5, page 267 for more details.
EPNUM = 111b is forbidden.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPRST6:0 - Endpoint FIFO Reset Bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 22.3, page 266 for more information
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/W
rite
Initial
Value
7
0
-
R
R
7
0
7
0
-
-
EPRST6
6
0
-
R/W
R
6
0
6
0
-
EPRST5
5
0
-
R/W
R
5
0
5
0
-
FNCERR
EPRST4
R
R/W
4
0
R
4
0
4
0
-
EPRST3
R/W
3
0
-
R
3
0
3
0
-
EPRST2
R/W
R/W
2
0
-
ATmega16/32U4
2
0
2
0
EPNUM2:0
EPRST1
R/W
R/W
1
0
-
1
0
1
0
EPRST0
R/W
R/W
0
0
-
0
0
0
0
UENUM
UDMFN
UERST
281

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