ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 310

• Manufacturer Part Number: ATMEGA32U4-MU
• Description: MCU AVR 32K FLASH 16MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Interface Type: EBI/I2S/SPI/TWI/USART/USB
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 5
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA32U4-16MU; ATMEGA32U4-16MU

24.9.2
7766F–AVR–11/10
ADC Control and Status Register A – ADCSRA
Table 24-4.
Note:
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
Bit
Read/Write
Initial Value
MUX5..0
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1. MUX5 bit make part of ADCSRB register
(1)
Single Ended Input
N/A
ADEN
R/W
Input Channel and Gain Selections (Continued)
7
0
ADSC
R/W
6
0
ADATE
R/W
5
0
Positive Differential Input
ADC4
ADC5
ADC6
ADC7
ADC4
ADC5
ADC6
ADC7
ADC4
ADC5
ADC6
ADC7
ADIF
R/W
4
0
ADIE
R/W
3
0
ADPS2
R/W
2
0
ADPS1
Negative Differential Input
ADC1
ADC1
ADC1
ADC1
ADC0
ADC0
ADC0
ADC0
ADC1
ADC1
ADC1
ADC1
R/W
1
0
ATmega16/32U4
ADPS0
R/W
0
0
ADCSRA
Gain
40x
40x
40x
40x
200x
200x
200x
200x
200x
200x
200x
200x
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