ATMEGA8HVA-4CKU Atmel, ATMEGA8HVA-4CKU Datasheet
ATMEGA8HVA-4CKU
Specifications of ATMEGA8HVA-4CKU
Related parts for ATMEGA8HVA-4CKU
ATMEGA8HVA-4CKU Summary of contents
Page 1
... TSOP • Operating Voltage: 1 • Maximum Withstand Voltage (High-voltage pins): 28V • Temperature Range: - 20°C to 85°C • Speed Grade: 1-4 MHz ® 8-bit Microcontroller (1) 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash ATmega8HVA ATmega16HVA Preliminary 8024A–AVR–04/08 ...
Page 2
... Pin Configurations 1.1 LGA Figure 1-1. Figure 1- DNC B CF2P C VREF DNC ATmega8HVA/16HVA 2 LGA - Pinout ATmega8HVA/16HVA LGA - pinout ATmega8HVA/16HVA PV2 PV1 NV CF2N VFET CF1P VREFGND VREG CF1N NI GND GND DNC PA1 PA0 GND OC OD DNC GND PC0 DNC GND VCC GND GND ...
Page 3
... CF1P/CF1N/CF2P/CF2N CF1P/CF1N/CF2P/CF2N are the connection pins for connecting external fly capacitors to the step-up regulator. 1.3.5 VREF Internal Voltage Reference for external decoupling. 1.3.6 VREFGND Ground for decoupling of Internal Voltage Reference. Do not connect to GND or SGND on PCB. 8024A–AVR–04/08 TSOP - pinout ATmega8HVA/16HVA ...
Page 4
... Port B also serves the functions of various special features of the ATmega8HVA/16HVA as listed in ”Alternate Functions of Port B” on page 1.3.10 PC0 Port C serves the functions of various special features of the ATmega8HVA/16HVA as listed in ”Alternate Functions of Port C” on page 1.3.11 OC High voltage output to drive Charge FET. 1.3.12 OD High voltage output to drive Discharge FET ...
Page 5
... Overview The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion appli- cations with focus on high security/authentication, accurate monitoring, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The chip allows very accurate accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µ ...
Page 6
... The ATmega8HVA/16HVA contains a 12-bit ADC that can be used to measure the voltage of each cell individually. The ADC can also be used to monitor temperature, either on-chip temper- ature using the built-in temperature sensor, external temperature using thermistors connected to dedicated ADC inputs. The ATmega8HVA/16HVA contains a high-voltage tolerant, open-drain IO pin that supports serial communication ...
Page 7
... Comparison Between ATmega8HVA and ATmega16HVA The ATmega8HVA and ATmega16HVA differ only in memory size and interrupt vector size. Table 2-1 Table 2-1. 3. Disclaimer All Min, Typ and Max values contained in this datasheet are preliminary estimates based on sim- ulations and characterization of other AVR microcontrollers manufactured on the same process technology ...
Page 8
... The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ATmega8HVA/16HVA 8 Block Diagram of the AVR Architecture ...
Page 9
... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega8HVA/16HVA has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 10
... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega8HVA/16HVA ...
Page 11
... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 7-2, each register is also assigned a data memory address, mapping them ATmega8HVA/16HVA 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
Page 12
... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value ATmega8HVA/16HVA 12 The X-, Y-, and Z-registers R27 (0x1B ...
Page 13
... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back ATmega8HVA/16HVA ”Interrupts” on page 52. The list also 13 ...
Page 14
... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega8HVA/16HVA 14 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ...
Page 15
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8024A–AVR–04/08 ; set Global Interrupt Enable ATmega8HVA/16HVA 15 ...
Page 16
... Figure 8-1. 8.3 SRAM Data Memory Figure 8-2 on page 17 The ATmega8HVA/16HVA is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For ATmega8HVA/16HVA 16 ”Memory Programming” on page 149 13 ...
Page 17
... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the ATmega8HVA/16HVA are all accessible through all these addressing modes. The Register File is described in page 11 ...
Page 18
... The I/O space definition of the ATmega8HVA/16HVA is shown in 175. All ATmega8HVA/16HVA I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 19
... I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega8HVA/16HVA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 20
... Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE ...
Page 21
... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 8024A–AVR–04/08 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 13 600 ATmega8HVA/16HVA Table 8-2 lists the typical programming Typ Programming Time 4.0 MHz OSC 3 ...
Page 22
... EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ATmega8HVA/16HVA 22 ; 8024A–AVR–04/08 ...
Page 23
... Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATmega8HVA/16HVA LSB GPIOR2 R/W R/W R/W R LSB GPIOR1 R/W R/W R/W R LSB GPIOR0 R/W R/W R/W R ...
Page 24
... The Voltage ADC is provided with a dedicated clock domain. The VADC clock is automatically prescaled relative to the System Clock Prescalers setting by the VADC Prescaler, giving a fixed VADC clock at 1 MHz. ATmega8HVA/16HVA 24 presents the principal clock systems in the AVR and their distribution. All of the clocks 34 ...
Page 25
... The device is shipped with this option selected. 2. The actual value of the added, selectable 4- 512 ms delay depends on the actual frequency of the “Ultra Low Power RC Oscillator”. See on page 165 ATmega8HVA/16HVA 144. Note that the frequency of the system 27. Additional Delay from Reset, Typical Values ...
Page 26
... Row from Software” on page 144 9.6 CPU, I/O, Flash, and Voltage ADC Clock The clock source for the CPU, I/O, Flash, and Voltage ADC is the calibrated Fast RC Oscillator. ATmega8HVA/16HVA 26 ”OSI – Oscillator Sampling Interface” on page 28 165.To provide a very good accuracy when used as a timing ” ...
Page 27
... CKOE bit in the MCU Control Register. The clock will not run in any sleep modes. 9.10 System Clock Prescaler The ATmega8HVA/16HVA has a System Clock Prescaler, used to prescale the Calibrated Fast RC Oscillator. The system clock can be divided by setting the ter” on page as the requirement for power consumption and processing power changes. This system clock will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 28
... Overview The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low Power RC (ULP) oscillators in ATmega8HVA/16HVA. OSI can be used to calibrate the Fast RC Oscilla- tor runtime with high accuracy. OSI can also provide an accurate reference for compensating the ULP Oscillator frequency drift. ...
Page 29
... Slow RC temperature coeffi- HOT ”Slow RC Oscillator” on page 26 ⋅ ------------------------------------------------------------------------------------------------------------------------------------------------ - FastRC SlowRC number of CPU cycles in n prescaled Slow RC periods ATmega8HVA/16HVA OSICSR Edge Detector (1) Fast RC Oscillator for details on how to is also stored in the signature row. These HOT for details. ...
Page 30
... The FCAL[7:5] bits determine the range of operation for the oscillator. Setting these bits to 0b000 gives the lowest frequency range, setting this bit to 0b111 gives the highest frequency range. The frequency ranges are overlapping. A setting of for instance FOSCCAL = 0x1F gives a higher frequency than FOSCCAL = 0x20. ATmega8HVA/16HVA 30 number of CPU cycles in n prescaled ULP RC periods ⋅ ...
Page 31
... Figure 30-1 on page 174 -– – CKOE PUD R R R/W R CLKPCE – – – R ATmega8HVA/16HVA ”OSI – Oscillator Sampling Interface” on page for typical characteristics of the FAST – – – – MCUCR – – CLKPS1 CLKPS0 R R R/W R ...
Page 32
... Read/Write Initial Value • Bits 7:5,3:2 – RES: Reserved bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. ATmega8HVA/16HVA 32 32. Note that writing to the System Clock Prescaler Select bits will abort any System Clock Prescaler Select ...
Page 33
... Setting this bit enables the Oscillator Sampling Interface. When this bit is cleared, the Oscillator Sampling Interface is disabled. Notes: 8024A–AVR–04/08 OSISEL Bit Description OSISEL0 The prescaler is reset each time the OSICSR register is written, and hence each time a new oscillator source is selected. ATmega8HVA/16HVA Oscillator source ULP Oscillator Slow RC Oscillator 33 ...
Page 34
... SRAM are unaltered when the device wakes up from any sleep mode except Power-off reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. ATmega8HVA/16HVA 34 presents the different clock systems in the ATmega8HVA/16HVA, and Wake-up Sources for Sleep Modes X X ...
Page 35
... External Interrupts CBP 8024A–AVR–04/08 Reset From all States Except Power-on Reset Sleep Interrupt Idle Black-out Detection Charger Connected Active Idle ( ATmega8HVA/16HVA RESET Reset Time-out Active Interrupt Sleep Sleep or Power-save Black-out Detection Black-out Detection Power-off Mode ADC Noise Reduction Power-save ( (3) ( (4) ( ...
Page 36
... CPU, Flash or any of the peripheral units running at the Fast internal Oscillator (RCOSC_FAST). If the current through the sense resistor is so small that the Coulomb Counter cannot measure it accurately, Regular Current detection should be enabled to reduce power consumption. The WDT keeps accurately track of the time so that battery self discharge can be calculated. ATmega8HVA/16HVA 36 Active Idle ...
Page 37
... I/O ”Digital Input Enable and Sleep Modes” on page 67 /2, the input buffer will use excessive power. REG ATmega8HVA/16HVA ”External Interrupts” on page 56 ”Clock Sources” on page ”PRR0 – Power Reduction Register 0” on page ) are stopped, the input buffers of the device will ADC 25 ...
Page 38
... Sensor” on page 117 10.7.8 FET Driver To minimize the power consumption in Power-save mode, the DUVR mode of the FET Driver should be disabled to make sure that the Fast RC Oscillator is stopped. ATmega8HVA/16HVA input pin can cause significant current even in active mode. Digital REG for details. ...
Page 39
... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero. • Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0 These bits select between the four available sleep modes as shown in Table 10-3. • ...
Page 40
... Bit 0 - PRVADC: Power Reduction V-ADC Writing a logic one to this bit shuts down the V-ADC. Before writing the PRVADC bit, make sure that the VADEN bit is cleared to minimize the power consumption. Note: V-ADC control registers can be updated even if the PRVADC bit is set. ATmega8HVA/16HVA 40 8024A–AVR–04/08 ...
Page 41
... Reset Sources The ATmega8HVA/16HVA has five sources of reset: • The Power-on Reset module generates a Power-on Reset when the Voltage Regulator starts up. • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 42
... Regulator. Before this happens the chip will be in Power-off mode and only the Charger Detect module is enabled. In order for the Charger Detect module to enable the Voltage Regulator, the voltage at the BATT pin must exceed the Power-On Threshold, V BATT pin exceeds V to Figure 11-2 on page See Figure 10-1 on page ATmega8HVA/16HVA 42 V REG Brown-out Detection Power-on FET ...
Page 43
... VFET_DUVR level. For high cell voltages, DUVR mode will not have any impact. DUVR mode may be disabled soon as the chip enters ACTIVE mode. 8024A–AVR–04/08 4/8/16/32/64/128/256/512 ms rises above V , ATmega8HVA/16HVA turns on the Voltage Regulator and BATT POT 41. While the chip is in reset, VREF calibration reg- ”DUVR – Deep Under-Voltage Recovery Mode operation” ...
Page 44
... Time-out period t page 46 Figure 11-4. Watchdog Reset During Operation 11.2.4 Brown-out Detection ATmega8HVA/16HVA has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level V REG hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level ...
Page 45
... Figure 11-5), the delay counter starts the MCU after the Time-out period t BOT BOT- RESET TIME-OUT INTERNAL RESET will always be well below the BOD level, V BLOT ATmega8HVA/16HVA BOT- increases above the trigger REG TOUT V BOT+ t TOUT drops below REG . BOT in Fig- ...
Page 46
... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.3.2 Overview ATmega8HVA/16HVA has an Enhanced Watchdog Timer (WDT). The WDT counts cycles of the Ultra Low Power RC Oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...
Page 47
... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. See “About Code Examples” on page 7. ATmega8HVA/16HVA 47 ...
Page 48
... Note: 1. See “About Code Examples” on page 7. Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATmega8HVA/16HVA 48 (1) r16, WDTCSR r16, (1<<WDCE) | (1<<WDE) ...
Page 49
... Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero. • Bit 4 – OCDRF: OCD Reset Flag This bit is set if a debugWIRE Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
Page 50
... Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 11-2 on page ATmega8HVA/16HVA 50 Watchdog Timer Configuration (1) WDE ...
Page 51
... The actual timeout value depends on the actual clock period of the Ultra Low Power RC Oscil- lator, refer to ”Ultra Low Power RC Oscillator” on page 26 ATmega8HVA/16HVA Number of WDT Typical Oscillator Cycles Time-out 2K cycles cycles cycles 64 ms 16K cycles 0.13s 32K cycles 0.26s 64K cycles ...
Page 52
... Interrupts 12.1 Overview ATmega8HVA/16HVA. For a general explanation of the AVR interrupt handling, refer to and Interrupt Handling” on page 12.2 Interrupt Vectors in ATmega8HVA . Table 12-1. Vector No the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. ...
Page 53
... CCADC_CONV ; CC-ADC Instantaneous Current Conversion Complete Handler CCADC_REC_CUR ; CC-ADC Regular Current Handler CCADC_ACC ; CC-ADC Accumulate Current Conversion Complete Handler EE_RDY ; EEPROM Ready Handler r16, ; Main program start high(RAMEND) SPH,r16 ; Set Stack Pointer to top of RAM r16, low(RAMEND) SPL,r16 ; Enable interrupts xxx ... ATmega8HVA/16HVA 53 ...
Page 54
... If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. ATmega8HVA/16HVA 54 Reset and Interrupt Vectors Program Address Source 0x0000 RESET 0x0002 BPINT 0x0004 VREGMON 0x0006 INT0 0x0008 INT1 0x000A INT2 0x000C ...
Page 55
... CCADC_CONV ; CC-ADC Instantaneous Current Conversion Complete Handler CCADC_REC_CUR ; CC-ADC Regular Current Handler CCADC_ACC ; CC-ADC Accumulate Current Conversion Complete Handler EE_RDY ; EEPROM Ready Handler r16, ; Main program start high(RAMEND) SPH,r16 ; Set Stack Pointer to top of RAM r16, low(RAMEND) SPL,r16 ; Enable interrupts xxx ... ATmega8HVA/16HVA 55 ...
Page 56
... Initial Value • Bits 7,6 – RES: Reserved Bits These bits are reserved in the ATmega8HVA/16HVA, and will always read as zero. • Bits 5:0 – ISC21, ISC20 - ISC01, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...
Page 57
... Initial Value • Bits 7:3 – RES: Reserved Bits These bits are reserved bits ins the ATmega8HVA/16HVA, and will always read as zero. • Bits 2:0 – INT2 - INT0: External Interrupt Request 2:0 Enable When an INT2 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register – ...
Page 58
... I/O Registers and bit locations are listed in One I/O Memory address location is allocated for each high voltage port, the Data Register – PORTx. The Data Register is read/write. Using the I/O port as General Digital Output is described in ital I/O” on page ATmega8HVA/16HVA 58 for a complete list of parameters. Pxn C pin ” ...
Page 59
... SLEEP CONTROL clkI/O: I/O CLOCK 1. WRx, RRx and RPx are common to all pins within the same port. clk mon to all ports. 62, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at ATmega8HVA/16HVA shows a functional description of one output port ( PORTxn ...
Page 60
... Figure 14-3. High Voltage Digital I/O Note: 1. WRx, RRx and RPx are common to all pins within the same port. clk Table 14-1 on page 61 indexes from generated internally in the modules having the alternate function. ATmega8HVA/16HVA 60 (1) Pxn DIEOExn DIEOVxn 1 ...
Page 61
... Port C Pins Alternate Functions Alternate Function PC0 INT0/ ICP0 (External Interrupt 0 or Timer/Counter0 Input Capture Trigger) relates the alternate functions of Port C to the overriding signals shown in 60. Overriding Signals for Alternate Functions in PC0 PC0/INT0 0 INT Enable 1 INT0 INPUT ATmega8HVA/16HVA Table 14-2. Figure 14- 61 ...
Page 62
... Register Description 14.5.1 PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 14.5.2 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value ATmega8HVA/16HVA – – – – – – – – N/A N/A N/A N/A ...
Page 63
... Characteristics” on page 165 Pxn C pin ”Register Description” on page 64. Many low voltage port pins are multiplexed with alternate functions for the ”Alternate Port Functions” on page ATmega8HVA/16HVA REG for a complete list R pu Logic See Figure "General Digital I/O" for Details 73 ...
Page 64
... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. ATmega8HVA/16HVA 64 SLEEP PUD: ...
Page 65
... Input 1 1 Input 0 X Output 1 X Output Figure 15-2, the PINxn Register bit and the preceding latch con- pd,max ATmega8HVA/16HVA Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 15-3 ...
Page 66
... The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. ATmega8HVA/16HVA 66 XXX PINxn ...
Page 67
... Figure 15-2 on page 64, the digital input signal can be clamped to ground at the ”Alternate Port Functions” on page ATmega8HVA/16HVA /2. REG 68. 67 ...
Page 68
... PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: ATmega8HVA/16HVA 68 or GND is not recommended, since this may cause excessive currents if the pin is CC shows how the port pin control signals from the simplified (1) PUOExn ...
Page 69
... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega8HVA/16HVA , I/O Fig- 69 ...
Page 70
... PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega8HVA/16HVA 70 Port A Pins Alternate Functions Port Pin Alternate Function ADC1/ SGND/ T1 (ADC Input Channel 1, Signal Ground or PA1 Timer/Counter1 Clock Input) ADC0/ SGND/ T0 (ADC Input Channel 0, Signal Ground or PA0 Timer/Counter0 Clock Input)) relates the alternate functions of Port A to the overriding signals shown in 68 ...
Page 71
... Port B Pins Alternate Functions Alternate Functions MISO/ INT2 (SPI Bus Master Input/Slave Output or External Interrupt 2 Input) MOSI/ INT1 (SPI Bus Master Output/Slave Input or External Interrupt 1 Input) SCK (SPI Bus Master clock Input) SS/ CKOUT (SPI Bus Master Slave select or Clock Output) 27. ATmega8HVA/16HVA Table 15-5. 71 ...
Page 72
... SPI SLAVE OUTPUT PTOE – DIEOE INT2 ENABLE DIEOV INT2 ENABLE SPI MSTR INPUT DI INT2 INPUT AIO – ATmega8HVA/16HVA 72 PB2/MOSI PB1/SCK SPE • MSTR SPE • MSTR PORTB2 • PUD PORTB1 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR SPE • ...
Page 73
... N/A N/A N/A N PORTB3 DDB3 PINB3 N/A N/A N/A N/A ATmega8HVA/16HVA – – – R/W R PORTA1 PORTA0 PORTA R R R/W R DDA1 DDA0 DDRA R R/ R/W R PINA1 PINA0 R R R/W R/W N/A N/A N/A N PORTB2 PORTB1 PORTB0 PORTB R/W R/W R/W R/W ...
Page 74
... However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. Figure 16-1. Prescaler for Timer/Counter ATmega8HVA/16HVA 74 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ...
Page 75
... T n Table 16-1 on page clk I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATmega8HVA/16HVA shows a functional Figure 16-2 ). The latch is transparent in the clk I/O for details Edge Detector clk_I/O ). The Tn Tn_sync (To Clock Select Logic) /2.5. ...
Page 76
... Bit 0 – PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. ATmega8HVA/16HVA ...
Page 77
... Overview Timer/Counter general purpose 8-/16-bit Timer/Counter module, with one/two Output Compare units and Input Capture functionality. ATmega8HVA/16HVA has two Timer/Counters, Timer/Counter0 and Timer/Counter1. The func- tionality for both Timer/Counters is described below. Timer/Counter0 and Timer/Counter1 have different Timer/Counter registers, as shown in The Timer/Counter general operation is described in 8-/16-bit mode. A simplified block diagram of the 8-/16-bit Timer/Counter is shown in I/O bits and I/O pins, are shown in bold ...
Page 78
... Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk details on clock sources and prescaler, see page 74 ATmega8HVA/16HVA 78 must be followed. Table 17-1 are also used extensively throughout the document. ...
Page 79
... DATA BUS count TCNTn Control Logic Increment or decrement TCNTn by 1. Timer/Counter clock, referred to as clk Signalize that TCNTn has reached maximum value. ”Timer/Counter Timing Diagrams” on page ATmega8HVA/16HVA TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) top in the following ...
Page 80
... Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in (TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then counter (TCNTn) is cleared. ATmega8HVA/16HVA 80 90. Table 17-2 on page 80 Timer/Counter Mode ...
Page 81
... As for the 16-bit Mode, the TOVn Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 8024A–AVR–04/08 TCNTn Period 1 2 for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock Table 17-2 on page 80 ATmega8HVA/16HVA OCnx Interrupt Flag Set 3 4 for bit settings. In CTC mode the counter is Table 81 ...
Page 82
... Input Capture mode the Output Compare Unit cannot be used as there are no free Output Compare Register(s). Even though the Input Capture register is called ICRn in this sec- tion referring to the Output Compare Register(s). For more information on how to access the 16-bit registers refer to ATmega8HVA/16HVA 82 ”Input Capture Unit” on page ”Input Capture Unit” on page ...
Page 83
... Measurement of an external signal duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be 8024A–AVR–04/08 ATmega8HVA/16HVA 83 ...
Page 84
... Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. Output Compare unit. Figure 17-5. Output Compare Unit, Block Diagram ATmega8HVA/16HVA 84 Timer/Counter0 Input Capture Source (ICS) Source ICP00: osi_posedge pin from OSI module ICP01: Port PC0 ” ...
Page 85
... TCNTn MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn shows the setting of OCFnA and OCFnB in Normal mode. ATmega8HVA/16HVA ) is therefore shown MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 85 ...
Page 86
... Input Capture mode the ICRn register formed by the OCRnA and OCRnB registers must be accessed with the temporary register 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATmega8HVA/16HVA 86 I/O Tn ...
Page 87
... Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn; ... 1. See “About Code Examples” on page 7. ATmega8HVA/16HVA 87 ...
Page 88
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See “About Code Examples” on page 7. The assembly code example returns the TCNTnH/L value in the r17:r16 register pair. ATmega8HVA/16HVA 88 8024A–AVR–04/08 ...
Page 89
... TCNTnH,r17 out TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; See “About Code Examples” on page 7. ATmega8HVA/16HVA 89 ...
Page 90
... Table 17-4 on page • Bits 2:0 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bit 0 – WGMn0: Waveform Generation Mode This bit controls the counting sequence of the counter, the source for maximum (TOP) counter ...
Page 91
... Note that the OCRnA is not writable in Input Capture mode. 8024A–AVR–04/ TCNTnL[7:0] R/W R/W R/W R TCNTnH[7:0] R/W R/W R/W R ”Accessing Registers in 16-bit Mode” on page OCRnA[7:0] R/W R/W R/W R 86. ATmega8HVA/16HVA R/W R/W R/W R R/W R/W R/W R 86. In 8-bit R/W R/W R/W R ”Accessing Registers in TCNTnL TCNTnH OCRnA 91 ...
Page 92
... Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter n Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter n occurs, i.e., when the TOVn bit is set in the n Interrupt Flag Register” on page ATmega8HVA/16HVA ...
Page 93
... Alternatively, TOVn is cleared by writing a logic one to the flag. When the SREG I-bit, TOIEn (Timer/Counter n Overflow Interrupt Enable), and TOVn are set, the Timer/Counter n Overflow interrupt is executed. 8024A–AVR–04/ ATmega8HVA/16HVA ICFn OCFnB OCFnA TOVn R/W R/W R/W R TIFRn 93 ...
Page 94
... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8HVA/16HVA and peripheral devices or between several AVR devices. The PRSPI bit in enable SPI module. Figure 18-1. SPI Block Diagram Note: 1 ...
Page 95
... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to nate Port Functions” on page 8024A–AVR–04/08 Table 18-1 on page 96. For more details on automatic port overrides, refer to 68. ATmega8HVA/16HVA Figure 18-2. The sys- SHIFT ENABLE /4. osc ” ...
Page 96
... DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega8HVA/16HVA 96 (1) SPI Pin Overrides ...
Page 97
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 7. ATmega8HVA/16HVA 97 ...
Page 98
... Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: 1. See “About Code Examples” on page 7. ATmega8HVA/16HVA 98 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR (1) ; 8024A–AVR–04/08 ...
Page 99
... Table 18-3 on page 101 and Table 18-4 on page SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 ATmega8HVA/16HVA 101, as done in Table 18-2. Leading Edge Trailing eDge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) ...
Page 100
... Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 ATmega8HVA/16HVA 100 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 LSB first (DORD = 1) LSB Bit 1 ...
Page 101
... Figure 18-3 and Figure 18-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 18-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega8HVA/16HVA CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 18-4 for an example ...
Page 102
... SPI Data Register. • Bit 5:1 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see be two CPU clock periods ...
Page 103
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8024A–AVR–04/ MSB R/W R/W R/W R ATmega8HVA/16HVA LSB R/W R/W R/W R SPDR Undefined 103 ...
Page 104
... Offset canceling by input polarity switching 19.2 Overview ATmega8HVA/16HVA features a dedicated Sigma-Delta ADC (CC-ADC) optimized for Coulomb Counting. By sampling the voltage across an external sense resistor R used to track the flow of current going into and out of the battery cells. Figure 19-1. Coulomb Counter Block Diagram ...
Page 105
... DATA4 will be lost because DATA3 reading is not completed within the limited period. 8024A–AVR–04/08 . Running in normal conversion mode, two data conversion output is provided. ~12ms settling INVALID DATA Table 19-3 ATmega8HVA/16HVA 3.9ms 3.9ms 7.8ms DATA 1 DATA 2 DATA 3 ...
Page 106
... The Regular Current Detection has a separate Interrupt and by setting the CADRCIE bit, this interrupt is enabled. Note that this Regular Current Detection interrupt cannot wake-up the CPU from sleep mode able to use the Regular Current Detection function in sleep modes, the ATmega8HVA/16HVA 106 125, 250, 500, ...
Page 107
... When the bit is zero, the polarity will be positive. 8024A–AVR–04/08 117. ”Slow RC Oscillator” on page CADEN CADPOL CADUB CADAS1 R/W R 117. ATmega8HVA/16HVA ”Voltage Reference for details CADAS0 CADSI1 CADSI0 CADSE R/W R/W R/W R Power-off, the CC-ADC is always dis- SENSE ” ...
Page 108
... The actual value depends on the actual frequency of the Slow RC oscillator, see 2. Sampling time ~ 12 ms. • Bit 0 - CADSE: CC-ADC Sampling Enable When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CCADC enters Regular Current detection mode. ATmega8HVA/16HVA 108 CC-ADC Accumulate Current Conversion Time CC-ADC Accumulate Current CADAS[1:0] ...
Page 109
... SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Inter- rupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag. 8024A–AVR–04/ – CADACIE CADRCIE CADICIE R R ATmega8HVA/16HVA – CADACIF CADRCIF CADICIF R R/W R/W R CADCSRB 109 ...
Page 110
... When CADAC0 is read, the CC-ADC Accumulate Current register is not updated until CADAC3 is read. Reading the registers in the sequence CADAC0, CADAC1, CADAC2, CADAC3 will ensure that consistent values are read. When a conversion is completed, all four registers must be read before the next conversion is completed, otherwise data will be lost. ATmega8HVA/16HVA 110 15 14 ...
Page 111
... Complete Interrupt Flag. 8024A–AVR–04/ CADRC[7:0] R/W R/W R/W R Table 19-3. Programmable Range for the Regular Current Level Minimum mΩ SENSE mΩ SENSE mΩ SENSE ATmega8HVA/16HVA R/W R/W R/W R Maximum Step size 0 6848 0 6848 0 1370 0 685 CADRC 26.9 26.9 5.4 2.7 ...
Page 112
... Interrupt on V-ADC Conversion Complete 20.2 Overview The ATmega8HVA/16HVA features a 12-bit Sigma-Delta ADC. The Voltage ADC (V-ADC) is connected to five different sources through the Input Multiplexer. There are two differential channels for Cell Voltage measurements. These channels are scaled 0.2x to comply with the Full Scale range of the V-ADC. In addition there are three single ended channels referenced to SGND ...
Page 113
... When measuring RT2, PA0 should be used as input channel and PA1 is automatically switched to SGND. 8024A–AVR–04/08 ”BGCCR – Bandgap Calibration C Register” on page OLD DATA INVALID DATA 162. Both termistors, RT1 and RT2, are connected through a common ATmega8HVA/16HVA 118. INVALID DATA ATA ”Operating Circuit” on page ”Operat- ...
Page 114
... Read/Write Initial Value • Bit 7:4 – RES: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bit 3:0 – VADMUX3:0: V-ADC Channel Selection Bits The VADMUX bits determine the V-ADC channel selection. See Table 20-1. ...
Page 115
... (VADCH/L VADC Cell – [mV] Cell = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - n ----- - (VADCH/L VADC ADCn Offset) 1 – ⋅ ADCn[mV] ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = 10 for details. The absolute temperature in Kelvin is given by: ATmega8HVA/16HVA – VADC[11:8] VADC[7: ⋅ Offset) VADC Cell Gain Calibration Word n n 16384 ⋅ VADC ADCn Gain Calibration Word 16384 ” ...
Page 116
... The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the PA1:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATmega8HVA/16HVA 116 ⋅ ...
Page 117
... Low Power Consumption 21.2 Overview A low power band-gap reference provides ATmega8HVA/16HVA with an accurate On-chip volt- age reference V Voltage Regulator, the V-ADC and the CC-ADC. The reference to the ADCs uses a buffer with external decoupling capacitor to enable excellent noise performance with minimum power con- sumption ...
Page 118
... BOD reset will occur recommended that the BGCC bits are updated with a step size allow the voltage regulator to reach the new level between each step, a delay of 20 µs should be added between each update of the BGCC values . ATmega8HVA/16HVA 118 1.1V ...
Page 119
... BGCR7 BGCR6 BGCR5 BGCR4 R/W R/W R/W R Temperature range of interest - Temperature [ ATmega8HVA/16HVA BGCR3 BGCR2 BGCR1 BGCR0 R/W R/W R/W R BGCRR is used to move the top of the VREF curve to the center of the tempearture range of interest BGCRR Figure 21-2 ...
Page 120
... Charge FET to ensure proper operating voltage at the VFET pin. This will ensure normal operation of the chip during 0-volt charging without setting the charger in quick-charge mode before the cell has reached a safe cell voltage. ATmega8HVA/16HVA 120 shows the Voltage Regulator block diagram with external components ...
Page 121
... ENABLE ENABLE CHARGER DETECT NFET DUALC_MODE DRIVER input voltage for 1-cell operation. Charger is connected 5V 3,3V V DUVR disabled charge pumping SW controlled T POT Chip Reset 4/8/16/32/64/128/256/512 ms ATmega8HVA/16HVA CF1 CF2 VIN VREF STEP-UP-REG VOUT CLK ENABLE VREG CREG VIN VREF LIN-REG VOUT ENABLE REG ...
Page 122
... Figure 22-3. Voltage Regulator block diagram, Linear mode only VFET BATT Figure 22-4. Voltage regulator operation and reset signals as a function of rising and falling Regulator operation DUVR mode Power-on Reset Chip Reset ATmega8HVA/16HVA 122 Voltage Regulator VIN VREF VREF CLK CLK ...
Page 123
... Bit 0 – ROCWIE: ROC Warning Interrupt Enable The ROCWIE bit enables interrupt caused by the Regulator Operating Condition Warning inter- rupt flag. 8024A–AVR–04/ ROCS - - - ATmega8HVA/16HVA ”Electrical Characteristics” on page ROCWIF ROCWIE ROCR R R R/W R 165, the 123 ...
Page 124
... Over-current Protection are automatically deactivated when the D-FET is disabled. The Charge Over-current and Charge High-current Protection are disabled when the C-FET is disabled. Note however that Charge Over-current Protection and Charge High-current Protection are never automatically disabled when the chip is operated in DUVR mode. ATmega8HVA/16HVA 124 C-FET Entry ...
Page 125
... Charge Over-current Protection will be acti- vated again. 23.6 Discharge High-current Protection If the voltage at the PI/NI pins is above the Discharge High-current Detection level for a time longer than High-current Protection Reaction Time, the chip activates Discharge High-current Protection. 8024A–AVR–04/08 ATmega8HVA/16HVA 125 ...
Page 126
... Battery Protection Parameter Lock Register Each protection has an Interrupt Flag. Each Flag can be read and cleared by the CPU, and each flag has an individual interrupt enable. All enabled flags are combined into a single battery pro- ATmega8HVA/16HVA 126 LOCK? LOCK? Battery Protection Battery Protection ...
Page 127
... Bit 5 – Res: Reserved Bits This bit are reserved and will always read as one. 8024A–AVR–04/ – – – – – – – SCD R ATmega8HVA/16HVA – – BPPLE BPPL R R R/W R DOCD COCD DHCD CHCD R/W R/W R/W R BPPLR BPCR ...
Page 128
... Bit 7 – Res: Reserved Bits This bit is reserved and will always read as zero. • Bit 6:0 – SCPT6:0: Short-circuit Protection Timing These bits control the delay of the Short-circuit Protection. The Short-circuit Timing can be set with a step size of 62.5 µs as shown in Table 23-2. ATmega8HVA/16HVA 128 – ...
Page 129
... See ”Electrical Characteristics” on page 2. Initial value additional delay T can be expected after enabling the corresponding FET. This is related to d the initialization of the protection circuitry. For the Discharge Over-Current protection, this ATmega8HVA/16HVA (1) ... (7.83 - 7.88 ms (7.89 - 7.95 ms ”Ultra Low Power RC Oscillator” on 165. ...
Page 130
... Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPHCTR register is written. Any writing to the BPHCTR register during this period will be ignored. ATmega8HVA/16HVA 130 applies when enabling the Discharge FET. For Charge Over-Current protection, this applies when enabling the Charge FET ...
Page 131
... Charge Over-current, as defined in SENSE 132. Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPCOCD register is written. Any writing to the BPCOCD register during this period will be ignored. ATmega8HVA/16HVA SCDL[7:0] ...
Page 132
... Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPCHCD register is written. Any writing to the BPCHCD register during this period will be ignored. Table 23-5. DL[7:0] ATmega8HVA/16HVA 132 R/W R/W ...
Page 133
... ATmega8HVA/16HVA Current for all Current Detection Levels SENSE = -10°C to 70°C) (Continued) A 7.5A 8.0A 8.5A 9.0A 9.5A 10.0A 11.0A 12.0A 13.0A 14.0A 15.0A 16.0A 17.0A 18.0A 19.0A Reserved ...
Page 134
... Once Discharge High-current violation is detected, DHCIF becomes set. The flag is cleared by writing a logic one to it. • Bit 0 – CHCIF: Charge High-current Protection Activated Interrupt Once Charge High-current violation is detected, CHCIF becomes set. The flag is cleared by writ- ing a logic one to it. ATmega8HVA/16HVA 134 ...
Page 135
... CREG, a BOD reset may occur before the Battery Protection delay timing has expired, causing the FETs to be disabled. 8024A–AVR–04/08 Figure 24-1. Power-off Mode BATTERY_PROTECTION Current Protection Timer DUVRD FET Control and CFE Status Register DFE ATmega8HVA/16HVA DUVR_OFF CHARGE_EN DISCHARGE_EN 135 ...
Page 136
... Overview The ATmega8HVA/16HVA includes a FET Driver. The FET Driver is designed for driving N- channel FETs used as high side switch 2-Cell Li-Ion battery pack. A block diagram of the FET driver is shown in When charging deeply over-discharged cells, the FET Driver will be operated in Deep Under- Voltage Recovery (DUVR) mode ...
Page 137
... DUVR mode operation is equivalent to normal enabling of the Charge FET (CFE=1). ATmega8HVA/16HVA should operate in DUVR mode until software detects that the cell has recovered from Deep Under-Voltage condition. When the cell has recovered from Deep Under- Voltage condition, software should first set CFE=1. This is safe now since the cell voltage is above minimum operating voltage ...
Page 138
... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero. • Bit 3 – DUVRD: Deep Under-voltage Recovery Disabled When the DUVRD is cleared (zero), the FET Driver will be forced to operate in Deep Under-volt- age Recovery DUVR mode ...
Page 139
... Figure 25-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the OSCSEL Fuses. 8024A–AVR–04/08 dW dW(RESET) GND shows the schematic of a target MCU, with debugWIRE enabled, and the emulator ATmega8HVA/16HVA 3.0 - 3.5V VCC 139 ...
Page 140
... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATmega8HVA/16HVA 140 will not work. CC ® ...
Page 141
... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 8024A–AVR–04/08 ATmega8HVA/16HVA 141 ...
Page 142
... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 26-1. Addressing the Flash During SPM Z - REGISTER Note: 1. The different variables used in ATmega8HVA/16HVA 142 Z15 ...
Page 143
... Table 27-2 on page 149 – – – – FLB7 FLB6 FLB5 FLB4 , the Flash program can be corrupted because the supply voltage is CC ATmega8HVA/16HVA LB2 LB1 for how the different settings of the – – LB2 LB1 Table 27-4 on page 150 ...
Page 144
... SLOW RC Period H SLOW RC Temp Prediction L SLOW RC Temp Prediction H ULP RC FRQ SLOW RC FRQ Reserved BGCCR Calibration Byte @ 25°C Reserved BGCRR Calibration Byte @ 25°C ATmega8HVA/16HVA 144 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction Signature Row Addressing. (1) (2) (3) (4) (6) (5) ...
Page 145
... Calibration word used to compensate for gain error in ADC1. 14. Calibration byte used to compensate for offset in ADC0 and ADC1. 15. Calibration word used to calculate the absolute temperature in Kelvin from a VTEMP conversion. 16. Hot tamperature used for factory calibration in °C. ATmega8HVA/16HVA Z-Pointer Address 12H 13H 14H ...
Page 146
... PCPAGE PCWORD Table 26-4. Variable PCMSB ATmega8HVA/16HVA 146 SPM Programming Time, f OSC Symbol Min Programming Time write Lock bits by SPM) Explanation of different variables used in pointer, ATmega8HVA. Corresponding Z-value 11 5 Z12 Z6 PC[11:6] Z12:Z7 PC[5:0] Z6:Z1 Explanation of different variables used in pointer, ATmega16HVA. Corresponding ...
Page 147
... Page Write operation – – SIGRD CTPB R R R/W R for details. ”EEPROM Write Prevents Writing to SPMCSR” on page 143 ATmega8HVA/16HVA Figure 26-1 and the mapping to the RFLB PGWRT PGERS SPMEN R/W R/W R/W R for details. ...
Page 148
... SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “100001”,“010001”, “001001”, “000101”, “000011” or “000001” in the lower six bits will have no effect. ATmega8HVA/16HVA 148 8024A–AVR–04/08 ...
Page 149
... Memory Programming 27.1 Program And Data Memory Lock Bits The ATmega8HVA/16HVA provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in be erased to “1” with the Chip Erase command. Table 27-1. ...
Page 150
... Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. ATmega8HVA/16HVA 150 Fuse High Byte Fuse High Byte Description – ...
Page 151
... These bytes reside in the signature address space. See for details. 27.5 Page Size Table 27-6. No. of Words in a Page and No. of Pages in the Flash, ATmega8HVA/16HVA Device Flash Size ATmega8HVA 4K words (8K bytes) ATmega16HVA 8K words (16K bytes) Table 27-7 ...
Page 152
... Low: > 2.2 CPU clock cycles for f High: > 2.2 CPU clock cycles for f 27.6.1 Serial Programming Algorithm When writing serial data to the ATmega8HVA/16HVA, data is clocked on the rising edge of SCK. When reading data from the ATmega8HVA/16HVA, data is clocked on the falling edge of SCK. See ”Serial Programming” on page 172 ...
Page 153
... WD_EEPROM WD_EEPROM 151 chip erased device, no 0xFF in the data file(s) need to be power off. CC Minimum Wait Delay Before Writing the Next Flash or EEPROM Location ATmega8HVA/16HVA before WD_FLASH Table 27-9 before issuing the next page (See Minimum Wait Delay 4 ...
Page 154
... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. ATmega8HVA/16HVA 154 and Figure 27-2 on page 155 describes the Instruction set ...
Page 155
... Serial Programming Instruction Byte 3 Byte 4 Adr LSB 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page N-1 Program Memory/ EEPROM Memory ATmega8HVA/16HVA Figure 27-2 on page Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 2 Byte 3 Adr MSB Adr LSB LSB SB Bit 15 B ...
Page 156
... High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, Lock bits and Fuse bits in the ATmega8HVA/16HVA. Figure 27-3. High-voltage Serial Programming Table 27-11. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode ...
Page 157
... High-voltage Serial Programming Algorithm To program and verify the ATmega8HVA/16HVA in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in 27.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in Serial (High-voltage) Programming mode: 1. Set Prog_enable pins listed in ...
Page 158
... Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATmega8HVA/16HVA, data is clocked on the rising edge of the serial clock, see page 173 Figure 27-4. Addressing the Flash which is Organized in Pages ...
Page 159
... Exit Programming mode by powering the device down bringing RESET pin to 0V. 8024A–AVR–04/08 MSB MSB MSB ”High-voltage Serial Programming” on page Table 27-14 on page 160. ATmega8HVA/16HVA LSB LSB LSB 160): Table 27-14 on page Table 27-14 on page Table 27-14 on 173. 160): ...
Page 160
... Table 27-14. High-voltage Serial Programming Instruction Set for ATmega8HVA/16HVA Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page Buffer ...
Page 161
... Table 27-14. High-voltage Serial Programming Instruction Set for ATmega8HVA/16HVA (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 Read EEPROM SII 0_0000_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0000_00 Write Fuse High SII 0_0100_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0000_00 Write Fuse Low SII 0_0100_1100_00 Byte SDO x_xxxx_xxxx_xx ...
Page 162
... OC VFET OD PV2 470 CP 0.1uF RP PV1 470 CP 0.1uF RP NV 470 Rpi PI 100 Rsense ATmega8HVA/16HVA Ci 0.010 0.1uF Rni NI 100 PA1/ADC1/SGND PA0/ADC0/SGND RT2 RT1 R1 10K VREF VREFGND GND CREF 1 uF Debug support. The value of the series resistor depends on the application. A value of 10k will ensure that programming and debugging operates correctly, but it must be determined by the end user that this does not affect the normal operation of the SPI interface ...
Page 163
... SPI interface. 2. PA1 should be connected to SNGD when measuring V(RT PA0 should be connected to SNGD when measuring V(RT ATmega8HVA/16HVA Rbatt 1k Rdf ...
Page 164
... NI Ci Current sense LP-filter capacitor (R +R )*Ci Current sense LP-filter time-constant PI NI Rsense Coulomb Counter sense resisotor Notes: 1. This is the absolute minimum capacitance required to ensure stable operation of the voltage regulator. ATmega8HVA/16HVA 164 Parameter Min R R@25°C B-constant 3000 R Worst-case Gain-error due 1.1 ...
Page 165
... Ground ...........................-0.5V to VFET + 1.0V Maximum Operating Voltage on VREG and VCC............. 4.5V Maximum Operating Voltage on VFET ................................ 9V 8024A–AVR–04/08 ATmega8HVA/16HVA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and ...
Page 166
... DC Characteristics Table 29-1. Electrical Characteristics Parameter Active Idle ADC Noise Reduction Supply Current Power-save Power-off ATmega8HVA/16HVA 166 ( -10°C to 70°C unless otherwise specified) A Condition 4.0 MHz, 4V ≤ V ≤ 8.4V, FET All PRR bits set. 1.0 MHz, 4V ≤ V ≤ 8.4V, FET All PRR bits set. 4.0 MHz, 4V ≤ ...
Page 167
... IOUT = 10 mA, CREG = 2.2 µF, VFET = 3.0V ESR = 0.1 Ω After calibration, at calibration temperature clk = 1 MHz VADC PV1 >= 1.5V (3)(7) 0.1V < V < 0.9V ADC -10° - 70°C CELL A ATmega8HVA/16HVA Min Typ 1.8 3.6 2.9 3.0 3.1 3.1 3.1 3.1 3.1 3 3.6 1.7 3 ...
Page 168
... Actual frequency measured at Atmel factory stored in signature row. 29.3 External Interrupt Characteristics Table 29-2. Asynchronous External Interrupt Characteristics Symbol Parameter Minimum pulse width for asynchronous external t INT interrupt ATmega8HVA/16HVA 168 ( -10°C to 70°C unless otherwise specified) (Continued) A Condition 26.9 µV Resolution 0.84 µV Resolution -100 mV < V < 100 mV ...
Page 169
... OH Pin low (absolute value) Pin high (absolute value -10°C to 70°C unless otherwise specified) A Condition 350 µA sink current ( < 400 pF ILmax b 0.1V < V < 0.9V BUS i ATmega8HVA/16HVA Typ. Max. (2) 0.3V CC (2) 0. 0 0 3.3V) under steady state conditions (non-tran ...
Page 170
... BLOT Note: 1. The voltage at the Pack + terminal will be slightly higher than V Pull-down current on the BATT pin in the range 50 - 110 uA and the R and the BATT pin gives a voltage drop 0.05 - 0.11V. BATT ATmega8HVA/16HVA 170 ( -10°C to 70°C unless otherwise specified) A Min. 1.9 3 ...
Page 171
... Mode Master Master Master Master Master Master Master Master Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave for serial programming requirements SCK SCK 4 5 MISO MSB 7 MOSI MSB ATmega8HVA/16HVA Min Typ See Figure 50% duty 3 0.5 • t sck • • 1 ...
Page 172
... Input) (Data Output) 29.8 Programming Characteristics 29.8.1 Serial Programming Figure 29-2. Serial Programming Timing Figure 29-3. Serial Programming Waveforms SERIAL DATA INPUT SERIAL DATA OUTPUT SERIAL CLOCK INPUT ATmega8HVA/16HVA 172 SS 9 SCK SCK 13 14 MOSI MSB 15 MISO MSB ...
Page 173
... Table 29-8. Serial Programming Characteristics, T Symbol Parameter 1/t Oscillator Frequency (ATmega8HVA/16HVA) CLCL t Oscillator Period (ATmega8HVA/16HVA) CLCL t SCK Pulse Width High SHSL t SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX t SCK Low to MISO Valid ...
Page 174
... These figures are not tested during manufacturing, and are added for illustration purpose only. Figure 30-1. Fast RC Oscillator frequency vs. OSCCAL value ATmega8HVA/16HVA 174 CALIBRATED FAST RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE 25 ˚ ...
Page 175
... ATmega8HVA/16HVA Bit 2 Bit 1 Bit 0 – – – – BPPLE BPPL COCD DHCD CHCD HCPT[5:0] OCPT[5:0] – – – COCIF DHCIF CHCIF ...
Page 176
... TCNT1L (0x83) Reserved – (0x82) Reserved – (0x81) TCCR1B – (0x80) TCCR1A TCW1 (0x7F) Reserved – (0x7E) DIDR0 – ATmega8HVA/16HVA 176 Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – – – – – – – – – ...
Page 177
... EEPROM Address Register Low Byte EEPROM Data Register – EEPM1 EEPM0 EERIE General Purpose I/O Register 0 – – – – – – – – ATmega8HVA/16HVA Bit 2 Bit 1 Bit 0 – – – VADMUX[3:0] – – – VADSC VADCCIF VADCCIE VADC Data Register High byte – ...
Page 178
... When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis- ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega8HVA/16HVA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
Page 179
... PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega8HVA/16HVA Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...
Page 180
... Load Program Memory LPM Rd, Z+ Load Program Memory and Post-Inc SPM Store Program Memory IN Rd Port ATmega8HVA/16HVA 180 Description then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)← ...
Page 181
... Note: 1. These instructions are only available in ATmega16HVA. 8024A–AVR–04/08 Description P ← Rr STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega8HVA/16HVA Operation Flags #Clocks None None None None None None ...
Page 182
... Body, 0.60 mm Pitch), Land Grid Array (LGA) Package. 28T 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) ATmega8HVA/16HVA 182 Ordering Code Package ATmega8HVA-4CKU 36CK1 ATmega8HVA-4TU 28T Package Type (1) Operation Range -20 to +85°C 8024A–AVR–04/08 ...
Page 183
... Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 36CK1 36-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package. 28T 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 8024A–AVR–04/08 ATmega8HVA/16HVA Ordering Code Package ATmega16HVA-4CKU 36CK1 ATmega16HVA-4TU 28T ...
Page 184
... Bottom View Notes: 1. This drawing is for general information only. 2. Metal pad dimensions > Dummy pad. TITLE 2325 Orchard Parkway 36CK1, 36-Pad, 6.50 x 3.50 x 0.73 mm Body, San Jose, CA 95131 0.60 mm Pitch, Land Grid Array (LGA) Package R ATmega8HVA/16HVA 184 D E Top View A1 BALL PAD CORNER ...
Page 185
... Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 8024A–AVR–04/08 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) ATmega8HVA/16HVA 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – ...
Page 186
... Errata 35.1 ATmega8HVA 35.1.1 Rev known errata. 35.2 ATmega16HVA 35.2.1 Rev known errata. ATmega8HVA/16HVA 186 8024A–AVR–04/08 ...
Page 187
... Datasheet Revision History 36.1 Rev. 8024A – 04/08 1. 8024A–AVR–04/08 Initial revision ATmega8HVA/16HVA 187 ...
Page 188
... ATmega8HVA/16HVA 188 8024A–AVR–04/08 ...
Page 189
... Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1LGA ...........................................................................................................................2 1.2TSOP .........................................................................................................................3 1.3Pin Descriptions .........................................................................................................3 2 Overview ................................................................................................... 5 2.1Comparison Between ATmega8HVA and ATmega16HVA .......................................7 3 Disclaimer ................................................................................................. 7 4 Resources ................................................................................................. 7 5 Data Retention .......................................................................................... 7 6 About Code Examples ............................................................................. 7 7 AVR CPU Core .......................................................................................... 8 7.1Overview ....................................................................................................................8 7.2ALU – Arithmetic Logic Unit .......................................................................................9 7.3Status Register ..........................................................................................................9 7.4General Purpose Register File ................................................................................11 7 ...
Page 190
... Description ..............................................................................................39 11 System Control and Reset .................................................................... 41 11.1Resetting the AVR .................................................................................................41 11.2Reset Sources .......................................................................................................41 11.3Watchdog Timer ....................................................................................................46 11.4Register Description ..............................................................................................49 12 Interrupts ................................................................................................ 52 12.1Overview ................................................................................................................52 12.2Interrupt Vectors in ATmega8HVA ........................................................................52 12.3Interrupt Vectors in ATmega16HVA ......................................................................54 13 External Interrupts ................................................................................. 56 13.1Overview ................................................................................................................56 13.2Register Description ..............................................................................................56 14 High Voltage I/O Ports ........................................................................... 58 14.1Overview ................................................................................................................58 14.2High Voltage Ports as General Digital I/O .............................................................59 14 ...
Page 191
... SPI – Serial Peripheral Interface ........................................................... 94 18.1Features ................................................................................................................94 18.2Overview ................................................................................................................94 18.3SS Pin Functionality ..............................................................................................99 18.4Data Modes ...........................................................................................................99 18.5Register Description ............................................................................................101 19 Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC ...... 104 19.1Features ..............................................................................................................104 19.2Overview ..............................................................................................................104 19.3Normal Operation ................................................................................................105 19.4Regular Current Detection Operation ..................................................................106 19.5Offset Canceling by Polarity Switching ................................................................107 8024A–AVR–04/08 ATmega8HVA/16HVA iii ...
Page 192
... High-current Protection ...........................................................................126 23.8Battery Protection CPU Interface ........................................................................126 23.9Register Description ............................................................................................127 24 FET Control ........................................................................................... 135 24.1Overview ..............................................................................................................135 24.2FET Driver ...........................................................................................................136 24.3DUVR – Deep Under-Voltage Recovery Mode operation ...................................137 24.4Register Description ............................................................................................138 25 debugWIRE On-chip Debug System .................................................. 139 25.1Features ..............................................................................................................139 25.2Overview ..............................................................................................................139 ATmega8HVA/16HVA iv 8024A–AVR–04/08 ...
Page 193
... I/O Lines characteristics ........................................................................169 29.5FET Driver Characteristics ..................................................................................170 29.6Power-on and Reset Characteristics ...................................................................170 29.7SPI Timing Characteristics ..................................................................................171 29.8Programming Characteristics ..............................................................................172 30 Typical Characteristics – Preliminary Data ....................................... 174 31 Register Summary ............................................................................... 175 32 Instruction Set Summary ..................................................................... 179 33 Ordering Information ........................................................................... 182 33.1ATmega8HVA ......................................................................................................182 33.2ATmega16HVA ....................................................................................................183 8024A–AVR–04/08 ATmega8HVA/16HVA v ...
Page 194
... Packaging Information ........................................................................ 184 34.136CK1 ..................................................................................................................184 34.228T ......................................................................................................................185 35 Errata ..................................................................................................... 186 35.1ATmega8HVA ......................................................................................................186 35.2ATmega16HVA ....................................................................................................186 36 Datasheet Revision History ................................................................. 187 36.1Rev. 8024A – 04/08 .............................................................................................187 Table of Contents....................................................................................... i ATmega8HVA/16HVA vi 8024A–AVR–04/08 ...
Page 195
... ATmega8HVA/16HVA vii ...
Page 196
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...