ATMEGA644A-PU Atmel, ATMEGA644A-PU Datasheet - Page 260

IC MCU AVR 64K FLASH 40PDIP

ATMEGA644A-PU

Manufacturer Part Number
ATMEGA644A-PU
Description
IC MCU AVR 64K FLASH 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA644A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG, TWI, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
22.9.5
8272A–AVR–01/10
DIDR0 – Digital Input Disable Register 0
• Bit 7, 5:3 – Res: Reserved Bits
T h e s e
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For ensuring compability with
future devices, these bits must be written zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 22-6.
• Bit 7..0 – ADC7D..ADC0D: ADC7..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x7E)
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
b i t s
ADC7D
ADC Auto Trigger Source Selections
R/W
7
0
ADTS1
0
0
1
1
0
0
1
1
ADC6D
a r e
R/W
6
0
ADC5D
ADTS0
R/W
r e s e r v e d
5
0
0
1
0
1
0
1
0
1
ADC4D
R/W
4
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
f o r
ADC3D
R/W
3
0
f u t u r e
ADC2D
R/W
2
0
ADC1D
R/W
1
0
u s e
ADC0D
R/W
0
0
i n
.
DIDR0
260
t h e

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