AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet
AT89C51RE2-SLRUM
Specifications of AT89C51RE2-SLRUM
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AT89C51RE2-SLRUM Summary of contents
Page 1
... Low EMI (inhibit ALE) • Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag • Power Control Modes: Idle Mode, Power-down Mode • Power Supply: 2.7V to 5.5V • Temperature Ranges: Industrial (-40 to +85°C) • Packages: PLCC44, VQFP44 Power Supply CC 8-bit Flash Microcontroller AT89C51RE2 ...
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... ISP capability or with software. The programming voltage is internally generated from the standard V The AT89C51RE2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10- source 4-level interrupt controller and three timer/counters. In addition, the AT89C51RE2 has a Programmable Counter Array, an XRAM of 8192 bytes, a ...
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... C51 CORE IB-bus Parallel I/O Ports & INT External Bus Ctrl Port 0 Port 1 Port 2 Port 3 Port4 (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Alternate function of Port 6 AT89C51RE2 (1) (1) (1) (1) Watch Dog Keyboard Timer2 POR PFD BOOT Regulator TWI SPI ...
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... PLCC44 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI RST P3.0/RxD_0 P6.0/RxD_1/SDA P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 P6.1/TxD_1/SCL 33 ALE 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 AT89C51RE2 VQFP44 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA P6.1/TxD_1/SCL ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 7663E–8051–10/08 ...
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... As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. I RXD_0 (P3.0): Serial input port O TXD_0 (P3.1): Serial output port I INT0 (P3.2): External interrupt 0 AT89C51RE2 ...
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... XTAL1 21 15 XTAL2 20 14 Tx_OCD 23 17 Rx_OCD 1 39 AT89C51RE2 6 Type Name and Function I INT1 (P3.3): External interrupt (P3.4): Timer 0 external input I T1 (P3.5): Timer 1 external input O WR (P3.6): External data memory write strobe O RD (P3.7): External data memory read strobe Port 6: Port 2-bit bidirectional I/O port with internal pull-ups ...
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... SFR Mapping The Special Function Registers (SFRs) of the AT89C51RE2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4, P5, P6 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
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... Interrupt Priority Control High 1 IPL1 B2h Interrupt Priority Control Low 1 Table 6. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 P4 C0h 8-bit Port 4 AT89C51RE2 RS1 POF SMOD1_0 SMOD0_0 - - M0 XRS2 EES ...
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... FPL3 FPL2 FPL1 FMR TF1 TR1 TF0 GATE1 C/T1# M11 - - - TF2 EXF2 RCLK - - - CCF4 CIDL WDTE - - AT89C51RE2 FPL0 FPS FMOD2 FMOD1 FSE FLOAD TR0 IE1 IT1 IE0 M01 GATE0 C/T0# M10 - - WTO2 WTO1 TCLK EXEN2 TR2 C/T2 T2OE 3 2 ...
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... SCON_1 C0h Serial Control 1 SBUF_1 C1h Serial Data Buffer 1 SADEN_1 BAh Slave Address Mask 1 SADDR_1 AAh Slave Address 1 BDRCON_1 BCh Baud Rate Control 1 BRL_1 BBh Baud Rate Reload 1 AT89C51RE2 ECOM0 CAPP0 CAPN0 ECOM1 CAPP1 CAPN1 - ECOM2 CAPP2 CAPN2 ECOM3 CAPP3 CAPN3 ...
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... SSC3 SSC2 SSC1 SSD7 SSD6 SSD5 SSD4 SSA7 SSA6 SSA5 SSA4 KBLS7 KBLS6 KBLS5 KBLS4 KBE7 KBE6 KBE5 KBE4 KBF7 KBF6 KBF5 KBF4 AT89C51RE2 CPOL CPHA SPR1 SPR0 SPTE UARTM SPTEIE MODFIE SPD3 SPD2 SPD1 SPD0 SSI SSAA SSCR1 SSCR0 SSC0 0 ...
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... SCON_0 98h 0000 0000 XXXX XXXX P1 90h 1111 1111 TCON 88h 0000 0000 0000 0000 P0 80h 0000 0111 1111 1111 0/8 AT89C51RE2 12 Non Bit addressable 1/9 2/A 3/B CH CCAP0H CCAP1H XXXX XXXX XXXX XXXX CL CCAP0L CCAP1L XXXX XXXX XXXX XXXX CMOD ...
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... Enhanced features on the UART and the timer 2 X2 Feature The AT89C51RE2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
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... The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See Table 15.) and SPIX2 bit in the CKCON1 register (see Table 16) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. AT89C51RE2 14 F OSC ...
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... Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the X2 peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting cleared. AT89C51RE2 T2X2 ...
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... AT89C51RE2 16 7663E–8051–10/08 ...
Page 17
... SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). SPIX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. AT89C51RE2 ...
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... There are two 16-bit DPTR registers that address the external memory, and a DPTR single bit called DPS = AUXR1.0 (see Table 17) that allows the program code to switch between them (Refer to Figure 4). Figure 4. Use of Dual Pointer 7 AUXR1(A2H) AT89C51RE2 18 0 DPS DPTR1 DPTR0 DPH(83H) DPL(82H) External Data Memory 7663E– ...
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... The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection DPS Cleared to select DPTR0. Set to select DPTR1. *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. AUXR1 EQU 0A2H LOOP: AT89C51RE2 GF2 DPS ...
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... In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C51RE2 20 7663E–8051–10/08 ...
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... Memory Architecture AT89C51RE2 features several on-chip memories: • Flash memory: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages. • Boot ROM: 4K bytes for boot loader. • 8K bytes internal XRAM Physical memory organisation Figure 5. Physical memory organisation Fuse Configuration Byte(1 byte) ...
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... AT89C51RE2 devices have expanded RAM in external data space configurable up to 8192bytes (see Table 18.). The AT89C51RE2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...
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... The stack may be located in the 256 lower bytes of the XRAM by activat- ing the extended stack mode (see EES bit in AUXR1). The M0 bit allows to stretch the XRAM timings set, the read and write pulses are extended from clock periods. This is useful to access external slow peripherals. 7663E–8051–10/08 AT89C51RE2 23 ...
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... Registers Table 18. AUXR Register AUXR - Auxiliary Register (8Eh Bit Number 4 Reset Value = XX01 1100b Not bit addressable AT89C51RE2 XRS2 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...
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... SP9 U2 - Bit Mnemonic Description Enable Extended Stack This bit allows the selection of the stack extended mode. EES Set to enable the extended stack Clear to disable the extended stack (default value) AT89C51RE2 SP Value FFh SP9=1 00h 512 SP Values rollover in: FFh 256B of IRAM + SP9=0 ...
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... Reset Value = 00XX 00X0b Not bit addressable AT89C51RE2 26 Bit Mnemonic Description Stack Pointer 9th Bit This bit has no effect when the EES bit is cleared. SP9 Set when the stack pointer belongs to the XRAM memory space Cleared when the stack pointer belongs to the 256bytes of internal RAM. Set and cleared by hardware ...
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... Up to 64K byte external program memory if the internal program memory is disabled (EA = 0). • Programming and erase voltage with standard Flash memory AT89C51RE2 features several on-chip memories: organization • Flash memory FM0: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages. ...
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... Physical memory Figure 9. Physical memory organisation organisation On-Chip Flash The AT89C51RE2 implements up to 128K bytes of on-chip program/code memory. Figure 9 and Figure 10 shows the partitioning of internal and external program/code memory spaces accord- memory ing to EA value. The memory partitioning of the 8051 core microcontroller is typical a Harvard architecture where program and data areas are held in separate memory areas ...
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... Logical MCU Physical Flash Address Address FFFFh 17FFFh upper 32K Bank 1 8000h 10000h On-Chip flash code memory External code memory AT89C51RE2 Logical MCU Physical Flash Logical MCU Address Address Address 1FFFFh FFFFh FFFFh upper 32K Bank 2 18000h 8000h ...
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... When EA=0, the on-chip flash memory is disabled and the MCU core can address only up to 64kByte of external memory (none of the on-chip flash memory FM0 banks or RM0 can be mapped and executed). Figure 11. Program/Code Memory Organization EA=0 Logical MCU Address FFFFh 0000h AT89C51RE2 30 External Physical Memory Address 0FFFFh 64K Common 00000h ...
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... Physical Logical MCU Address Address 17FFFh FFFFh Bank 1 Bank 2 10000h 8000h On-Chip ROM memory (RM0) On-Chip flash code memory External code memory AT89C51RE2 Physical Logical MCU Address Address 1FFFFh FFFFh Bank 3 (Ext) 18000h 8000h Logical MCU Address 1000h ...
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... ISP operation. The hardware conditions allows to force the enter in ISP mode whatever the configurations bits. Figure 12. Boot Reset vector configuration EA pin Hardware conditions 0 X YES 1 NO AT89C51RE2 32 BRV2-0 X External Code at address 0x0000 X RM0 at address 0x0000 (ATMEL Bootloader FM0 at address 0x0000 with bank0 mapped ...
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... Table 19. Hardware Security Byte (HSB Bit Number 7 6-4 3 2-0 7663E–8051–10/ Bit Mnemonic Description - Unused - Reserved - Unused FM0 Memory Lock Bits FLB2-0 See Table 32 on page 52 AT89C51RE2 FLB2 FLB1 0 FLB0 33 ...
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... Fuse Configuration Byte The Fuse configuration byte is a part of FM0. (FCB) The 8 bits read/written by software (from FM0 or RM0) and written by hardware in parallel mode. Table 20. Fuse Configuration Byte (FCB Bit Number 7 6-3 2-0 AT89C51RE2 Bit Mnemonic Description X2 Mode Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset X2 Unprogrammed (‘ ...
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... Load column latch (user Flash) Write Read RM0 Load column latch (boot ROM) Write External memory Read Load column latch or EA=1, Bank3 Write Depends of general lock bits configuration AT89C51RE2 FM0 RM0 (boot ROM) (user Flash) ok Denied ok N.A. ok (pseudo idle mode ...
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... BMSEL Register Table 22. BMSEL Register BMSEL Register (S:92h) Bank Memory Select 7 MBO2 Bit Number 7-5 4-3 2-0 Reset Value= 0000 0YYYb (where YYY depends on BRV2:0 value in Fuse Configuration Byte) AT89C51RE2 MBO1 MBO0 Bit Mnemonic Description Memory Bank Operation These bits select the target memory bank for flash write or read operation. These bits allows to read or write the on-chip flash memory from one upper 32K bytes to another one ...
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... The MOVX @DPTR, A instruction writes in the columns latches space FPS When this bit is cleared: The MOVX @DPTR, A instruction writes in the regular XDATA memory space Flash Mode These bits allow to select the target memory area and operation on FM0 FMOD2:0 See Table 25. AT89C51RE2 FPS FMOD2 FMOD1 0 ...
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... Flash Status Register 7 FMR Bit Number 7 6 Reset Value= ‘R’xxx x000b Where ‘R’ depends on the reset conditions: If RM0 is executed after Reset R=1, if FM0 is exe- cuted after reset R=0 AT89C51RE2 Bit Mnemonic Description Flash Movc Redirection When code is executed from RM0 (and only RM0), this bit allow the MOVC instruction to be redirected to FM0 ...
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... Writing is possible from 0000h to FFFFh, address bits are used to select an address within a page while bits are used to select the programming address of the page. Table 25. .FM0 blocks select bits FMOD2 7663E–8051–10/08 FMOD1 FMOD0 AT89C51RE2 Adressable Space 0 FM0 array(0000h-FFFFh) 1 Extra Row(00h-80h) 0 Erase FM0 1 Column latches reset 0 HSB 1 FCB 0 Reserved 1 39 ...
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... This sequence is 5xh followed by Axh. Table 26 summarizes the memory spaces to program according to FMOD2:0 bits. Table 26. FM0 XAF FM0 Erase FM0 Reset FM0 Column Latches HSB FCB Reserved Reserved Note: AT89C51RE2 40 FM0 Programming Sequences Write to FCON FPL3:0 FPS FMOD2 ...
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... Load Accumulator register with the data to write. • Execute the MOVX @DPTR, A instruction, and only this one (no MOVX @Ri, A). • If needed loop the last three instructions until the page is completely loaded. • Unmap the column latch if needed (it can be left mapped) and Enable Interrupt 7663E–8051–10/08 AT89C51RE2 41 ...
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... Launch the programming by writing the data sequence 50h followed by A0h in FCON register. The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. AT89C51RE2 42 Column Latches Save & Disable IT Select target bank Column Latches Reset FCON= 53h (FPS=0) ...
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... Figure 13 Save & Disable IT EA= 0 Launch Programming FCON= 50h FCON= A0h FBusy Cleared? Clear Mode FCON = 00h End Programming Restore IT AT89C51RE2 XROW Programming Column Latches Loading see Figure 13 Save & Disable IT EA= 0 Launch Programming FCON= 51h FCON= A1h FBusy Cleared? ...
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... Set FPS and map FCB (FCON = 0x0D) • Save and disable the interrupts. • Load DPTR at address 0000h • Load Accumulator register with the data to load. • Execute the MOVX @DPTR, A instruction. AT89C51RE2 44 HSB Programming Save & Disable IT EA= 0 FCON = 0Ch Data Load DPTR= 00h ...
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... FCB Programming Save & Disable IT EA= 0 FCON = 0Dh Data Load DPTR= 00h ACC= Data Exec: MOVX @DPTR, A Launch Programming FCON= 55h FCON= A5h FBusy Cleared? Clear Mode FCON = 00h End Programming RestoreIT AT89C51RE2 45 ...
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... In addition, the user application can reset the columns latches space manually. The fol- lowing procedure is used to reset the columns latches space Launch the programming by writing the data sequence 53h followed by A3h in FCON register (from FM0 and RM0). AT89C51RE2 46 7663E–8051–10/08 ...
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... In this case, if columns latches were previously loaded they are reset: FLOAD bit in FSTA regis- ter should be reset after power down mode power down mode is requested during flash programming (FBUSY=1), all power down sequence instructions should be ignored until the end of flash process. 7663E–8051–10/08 AT89C51RE2 47 ...
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... Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h. • Clear FCON to unmap the Hardware Security Byte. AT89C51RE2 48 FCON is supposed to be reset when not needed. XRAW Reading XRAW Mapping ...
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... Map the FCB by writing 05h in FCON register. • Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h. • Clear FCON to unmap the Hardware Security Byte. HSB Reading Procedure 7663E–8051–10/08 AT89C51RE2 HSB Reading HSB Mapping FCON = 04h Data Read DPTR= 0000h ACC= 00h ...
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... The table below provide the different kind of memory which can be accessed from different code location. Table 27. Cross Memory Access boot RM0 FM0 External memory BANK3 Sharing Instructions Table 28. Instructions shared Action Read Write Note: AT89C51RE2 50 XRAM Action RAM ERAM boot RM0 Read ok ok Write ok ok Read ok ...
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... FPS of FCCON FBS FMOD2:0 (Fetch MBO DPTR (Target) X < 0x8000 X X >= 0x8000 AT89C51RE2 XRAM ERAM CL FM0 winner winner winner MBO MOVC A,@A+DPTR (Target) X Read External Code MOVC A,@A+DPTR Depends on FLB2:0 Can Returns Random value, for secured part. External code read 51 ...
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... Table 32. Program Lock Bit FLB2-0 Security level Program Lock bits U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be programmed after verification. AT89C51RE2 52 Program Lock Bits FLB0 FLB1 FLB2 Protection Description program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory sampled and latched on reset, and further parallel programming of the Flash is disabled ...
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... The bootloader manages a communication between a host platform running an ISP tool and a AT89C51RE2 target. The bootloader implemented in AT89C51RE2 is designed to reside in the dedicated ROM bank. This memory area can only be executed (fetched) when the processor enters the boot process. The implementation of the bootloader is based on standard set of libraries including INTEL hex based protocol, standard communication links and ATMEL ISP command set ...
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... EA=1 and PSEN=0) are received by the processor or when no hardware condition is applied and the BRV2:0 is configured ‘011’. Communication link Two interfaces are available for ISP: detection • UART0 • OCD UART AT89C51RE2 BRV=’011’ Yes Start Bootloader No No BRV=’100’ ...
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... Figure 20. Communication link Detection Notes: 7663E–8051–10/08 Detection Start Interface 1 Yes Interface 2 Yes SF: Start of Frame (‘0’ = detected; ‘1’ = not detected AT89C51RE2 implementation, Interface 1 refers to UART0 and Interface 2 refers to the OCD UART interface. AT89C51RE2 Interface 2 Interface 1 Initialisation Initialisation Start Bootloader 55 ...
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... Record Type: – • Data/Info: – • Checksum: – AT89C51RE2 56 Record length Load Offset 1 byte 2 bytes Record Mark is the start of frame. This field must contain’:’. Record length specifies the number of Bytes of information or data which follows the Record Type field of the record. ...
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... Each command flow may end with: 7663E–8051–10/08 Host Init Communication If (not received “U”) Else Communication Opened ":" ":" AT89C51RE2 Bootloader “U” Performs Autobaud Sends Back ‘U’ Character “U” Bootloader If (not received ":") Else ...
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... If checksum error • “L”: If read security is set • “P”: If program security is set • “.”: If command ok • byte + “.”: read byte ok AT89C51RE2 58 7663E–8051–10/08 ...
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... Record Record Type Length Offset Data[0] 04h 05h 0000h Start Address Record Record Type Length 02h 02h 04h 02h AT89C51RE2 Data[1] Data[2] Data[3] Data[4] 00h End Address 01h Offset Data[0] Data[1] start Page (4 00h address bits Memory 0000h Page ...
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... Security is set Starting application The application can only be started by a Watchdog reset. No answer is returned by the bootloader. Requests from Host Command Start application with watchdog AT89C51RE2 60 Record Record Type Length Offset Data[0] ...
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... Memory/Information Family * the coding number doesn’t include any information on the authorized address range of the fam- ily. A summary of these addresses is available in appendix (See “Address Mapping” on page 67.) AT89C51RE2 coding* name 0 MEM_FLASH ...
Page 62
... The following table summarizes the memory spaces for which the select page command can be applied. Table 35. Memory space & Select page FLASH AT89C51RE2 62 command allows to define a page number in the selected area. A page is Memory/Information Family Comments/Restriction page 0 (0-> ...
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... Memory/Information Family Command 111 Allowed write from FLB2:0 111 Allowed Forbidden Forbidden Forbidden AT89C51RE2 Comments/Restriction need security level check only a higher level can be write Security level (HSB) FLB2:0 110 101 Forbidden Forbidden Forbidden Security level (HSB) to FLB2:0 ...
Page 64
... The erasing command on the Flash memory: • erases the four physical flash memory banks (from address 0000h to 1FFFFh). • the HSB (Hardware Security Byte) is set at NO_PROTECTION: – AT89C51RE2 64 Memory/Information Family FLB2.0 = ‘111’ Comments/Restriction need security level check 7663E–8051–10/08 ...
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... The blank check operation is only possible if the HSB (Hardware Security Byte) has a security level lower than or equal to ‘2’ (FLB2.0 = ‘110’) Table 41. Flash Blank check Authorization Summary Blank Check 7663E–8051–10/08 Memory/Information Family Command 111 Allowed AT89C51RE2 Comments/Restriction need security level check Security level (HSB) FLB2:0 110 101 Allowed Forbidden ...
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... Accesses must be done byte per byte according to the address definition SIGNATURE All the field from the SIGNATURE family can be read from the bootloader. Each signature infor- mation shall be read unitary. Accesses must be done byte per byte according to the address definition AT89C51RE2 66 Memory/Information Family Command 111 Allowed ...
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... Memory/Parameter coding FLASH 0 HSB 7 FCB 8 Bootloader revision Boot id1 3 Boot id2 Manuf. code Family code 6 Product name Product rev AT89C51RE2 Data[0] Data[1] Data[ Page (4 00h x bits Memory Page x space Start Address End Address 00h FFh 00h ...
Page 68
... Timers/Counters The AT89C51RE2 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a pro- grammed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin ...
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... CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg 7663E–8051–10/08 0 THx (8 bits) 1 TRx TCON reg 0 THx (8 bits) 1 TRx TCON reg AT89C51RE2 Timer x TLx Overflow Interrupt TFx (5 bits) Request TCON reg Timer x TLx Overflow Interrupt TFx (8 bits) Request TCON reg 69 ...
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... Timer 1 is restricted when Timer mode 3. Figure 26. Timer/Counter 0 in Mode 3: Two 8-bit Counters FTx ÷ 6 CLOCK T0 C/T0# TMOD.2 INT0# GATE0 TMOD.3 FTx ÷ 6 CLOCK See the “Clock” section AT89C51RE2 bits bits) TRx TCON reg 0 (8 bits) 1 TR0 TCON.4 (8 bits) TR1 TCON ...
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... Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt rou- tine. Interrupts are enabled by setting globally enabled by setting EA bit in IEN0 register. 7663E–8051–10/08 AT89C51RE2 bit in IEN0 register. This assumes interrupts are ETx 71 ...
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... Figure 27. Timer Interrupt System AT89C51RE2 72 Timer 0 TF0 Interrupt Request TCON.5 ET0 IEN0.1 Timer 1 TF1 Interrupt Request TCON.7 ET1 IEN0.3 7663E–8051–10/08 ...
Page 73
... Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. Interrupt 0 Type Control Bit IT0 Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0. AT89C51RE2 IE1 IT1 ...
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... Timer/Counter Mode Control Register 7 GATE1 Bit Number Notes: 1. Reloaded from TH1 at overflow. Reset Value = 0000 0000b AT89C51RE2 C/T1# M11 M01 Bit Mnemonic Description Timer 1 Gating Control Bit GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. ...
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... Bit Mnemonic Description High Byte of Timer – – – Bit Mnemonic Description Low Byte of Timer – – – Bit Mnemonic Description High Byte of Timer 1. AT89C51RE2 – – – – – – – – – 0 – 0 – 0 – 75 ...
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... Table 51. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register 7 – Bit Number 7:0 Reset Value = 0000 0000b AT89C51RE2 – – – Bit Mnemonic Description Low Byte of Timer – – – 7663E–8051–10/08 0 – ...
Page 77
... Timer 2 The Timer 2 in the AT89C51RE2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 52) and T2MOD (Table 53) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input ...
Page 78
... To start the timer, set TR2 run control bit in T2CON register possible to use Timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and RCAP2L registers. AT89C51RE2 78 F CLK PERIPH ...
Page 79
... Figure 29. Clock-Out Mode C/ 7663E–8051–10/08 :6 FCLK PERIPH T2 T2EX AT89C51RE2 TR2 T2CON 2 TL2 TH (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 79 ...
Page 80
... Table 52. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT89C51RE2 EXF2 RCLK TCLK Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
Page 81
... The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. AT89C51RE2 T2OE 0 DCEN ...
Page 82
... CPS1 and CPS0 bits in the CMOD register (Table 54) and can be programmed to run at: • 1/6 the • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C51RE2 82 ÷ ) CLK PERIPH ÷ ) CLK PERIPH PCA component 16-bit Counter ...
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... Figure 30. PCA Timer/Counter Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 Idle 7663E–8051–10/ bit up/down counter CIDL CPS1 CPS0 WDTE CF CR CCF4 CCF3 CCF2 CCF1 CCF0 AT89C51RE2 To PCA modules overflow It CL CMOD ECF 0xD9 CCON 0xD8 83 ...
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... ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. AT89C51RE2 WDTE ...
Page 85
... Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 1 interrupt flag CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 interrupt flag CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. AT89C51RE2 CCF3 CCF2 CCF1 0 CCF0 85 ...
Page 86
... If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 56 shows the CCAPMn settings for the various PCA functions. AT89C51RE2 CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn ...
Page 87
... Cleared to disable the CEXn pin to be used as a pulse width modulated output. Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt Cleared to disable compare/capture flag CCFn in the CCON register to generate an CCF0 interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. AT89C51RE2 MATn TOGn PWMn ...
Page 88
... CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh Bit Number 7-0 Reset Value = 0000 0000b Not bit addressable AT89C51RE2 88 CAPPn CAPNn MATn TOGn ...
Page 89
... Table 61. CL Register CL - PCA Counter Register Low (0E9h Bit Number 7-0 Reset Value = 0000 0000b Not bit addressable 7663E–8051–10/ Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnL Value Bit Mnemonic Description PCA counter - CH Value Bit Mnemonic Description PCA Counter - CL Value AT89C51RE2 ...
Page 90
... CCAPMn register. The PCA timer will be compared to the module's capture regis- Timer/ Compare ters and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn Mode (CCAPMn SFR) bits for the module are both set (See Figure 33). AT89C51RE2 90 CCF4 CCF3 CCF2 CCF1 CCF0 Capture CAPPn ...
Page 91
... A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. 7663E–8051–10/08 CF CCF4 CCF3 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE AT89C51RE2 CCON 0xD8 CCF2 CCF1 CCF0 PCA IT RESET * CCAPMn 0xDA to 0xDE CMOD CPS1 CPS0 ECF 0xD9 91 ...
Page 92
... When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT89C51RE2 ...
Page 93
... Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. 7663E–8051–10/08 CCAPnH Overflow CCAPnL Enable 8 bit comparator CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C51RE2 “0” CEXn “1” CCAPMn 0xDA to 0xDE 93 ...
Page 94
... Serial I/O Port The serial I/O ports in the AT89C51RE2 are compatible with the serial I/O port in the 80C52. They provide both synchronous and asynchronous communication modes. They operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different ...
Page 95
... SMOD0=1 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect). SADDR0101 0110b SADEN1111 1100b Given0101 01XXb AT89C51RE2 Data byte Stop bit Data byte ...
Page 96
... On reset, the SADDR and SADEN registers are initialized to 00h the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT89C51RE2 96 SADEN1111 1010b Given1111 0X0Xb ...
Page 97
... Reset Value = 0000 0000b Not bit addressable Table 64. SADEN_1 Register SADEN_1 - Slave Address Mask Register UART 1(BAh) 7 Reset Value = 0000 0000b Not bit addressable Table 65. SADDR_1 Register SADDR_1 - Slave Address Register UART 1(AAh) 7 Reset Value = 0000 0000b Not bit addressable 7663E–8051–10/ AT89C51RE2 ...
Page 98
... The Baud Rate Generator for transmit and receive clocks can be selected separately via the Selection for T2CON and BDRCON_0 registers. UART 0 for Mode 1 Figure 40. Baud Rate Selection for UART 0 and 3 Table 66. Baud Rate Selection Table UART 0 TCLK (T2CON AT89C51RE2 98 TIMER1 TIMER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 TIMER_BRG_TX 0 ...
Page 99
... TIMER1 TIMER_BRG_TX 0 TIMER2 1 TCLK INT_BRG1 RCLK TBCK_1 (T2CON) (BDRCON_1 AT89C51RE2 Clock_1 1 RBCK_1 Clock_1 TBCK_1 RBCK_1 Clock Source Clock Source (BDRCON_1) UART Tx_1 UART Rx_1 0 Timer 1 0 Timer 2 0 Timer 1 0 Timer 2 0 INT_BRG_1 0 INT_BRG_1 1 Timer 1 INT_BRG_1 1 Timer 2 INT_BRG_1 1 INT_BRG_1 INT_BRG_1 Timer 1 ...
Page 100
... Internal Baud Rate The AT89C51RE2 implements two internal baudrate generators. Each one is dedicated to the Generator (BRG) corresponding UART. The configuration and operating mode for both BRG are similar. When an internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow ...
Page 101
... Set by hardware at the end of the 8th bit time in mode the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. 0 RI_0 Set by hardware at the end of the 8th bit time in mode 0, see Figure 38. and Figure 39. in the other modes. AT89C51RE2 TB8_0 RB8_0 Mode Description Baud Rate ...
Page 102
... SCON_1 - Serial Control Register for UART 1(C0h) 7 FE/SM0_1 Bit Number Reset Value = 0000 0000b Bit addressable AT89C51RE2 102 SM1_1 SM2_1 REN_1 Bit Mnemonic Description Framing Error bit (SMOD0=1 ) Clear to reset the error state, not cleared by a valid stop bit. FE_1 Set by hardware when an invalid stop bit is detected. ...
Page 103
... F = 16. 384 MHz OSC BRL 4800 247 2400 238 1200 220 600 185 AT89C51RE2 F OSC Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0.63 178 0.31 100 1. OSC Error (%) BRL 1.23 243 1 ...
Page 104
... Table 74. SBUF_1 Register SBUF - Serial Buffer Register for UART 1(C1h) 7 Reset Value = XXXX XXXXb Table 75. BRL_1 Register BRL - Baud Rate Reload Register for the internal baud rate generator 1 (BBh) 7 Reset Value = 0000 0000b AT89C51RE2 104 7663E–8051–10/ ...
Page 105
... Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. CP/RL2# Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. AT89C51RE2 EXEN2 TR2 C/T2# Description ). ...
Page 106
... Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT89C51RE2 106 SMOD0_0 - POF Bit Mnemonic Serial port Mode bit 1 for UART SMOD1_0 Set to select double baud rate in mode ...
Page 107
... Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART SRC_0 Cleared to select F /12 as the Baud Rate Generator (F OSC Set to select the internal Baud Rate Generator for UARTs in mode 0. AT89C51RE2 TBCK_0 RBCK_0 SPD_0 / mode). ...
Page 108
... BDRCON - Baud Rate Control Register (BCh) 7 SMOD1_1 Bit Number Reset Value = 0000 0000b Not bit addressable AT89C51RE2 108 SMOD0_1 - BRR_1 Bit Mnemonic Description Serial port Mode bit 1 for UART 1 SMOD1_1 Set to select double baud rate in mode Serial port Mode bit 0 for UART 1 SMOD0_1 Cleared to select SM0 bit in SCON register ...
Page 109
... Interrupt The AT89C51RE2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), two serial ports interrupts, SPI interrupt, Keyboard System interrupt and the PCA global interrupt. These interrupts are shown in Figure 44. Figure 44. Interrupt Control System ...
Page 110
... If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simul- taneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. AT89C51RE2 110 iph. x ipl. x ...
Page 111
... Cleared to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. AT89C51RE2 ET1 EX1 ET0 0 EX0 111 ...
Page 112
... Table 82. IPL0 Register IPL0 - Interrupt Priority Register (B8h Bit Number Reset Value = X000 0000b Bit addressable AT89C51RE2 112 PPCL PT2L PSL Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit PPCL Refer to PPCH for priority level ...
Page 113
... PX1H PX1L Priority Level 0 0 Lowest PX1H Highest Timer 0 overflow interrupt Priority High bit PT0H PT0L Priority Level 0 0 Lowest PT0H Highest External interrupt 0 Priority High bit PX0H PX0L Priority Level 0 0 Lowest PX0H Highest AT89C51RE2 PT1H PX1H PT0H 0 PX0H 113 ...
Page 114
... Table 84. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Number Reset Value = XXXX 00x0b Bit addressable AT89C51RE2 114 Bit Mnemonic Description - Reserved - Reserved - Reserved - Reserved Serial port 1 Enable bit ES_1 Cleared to disable serial port interrupt. Set to enable serial port interrupt. SPI interrupt Enable bit Cleared to disable SPI interrupt ...
Page 115
... Refer to PSH_1 for priority level. SPI interrupt Priority bit SPIL Refer to SPIH for priority level. TWI interrupt Priority bit TWIL Refer to TWIH for priority level. Keyboard interrupt Priority bit KBDL Refer to KBDH for priority level. AT89C51RE2 PSL_1 SPIL TWIL 0 KBDL 115 ...
Page 116
... Table 86. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Number Reset Value = XXXX 00X0b Not bit addressable AT89C51RE2 116 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...
Page 117
... Reset 1 INT0 2 Timer 0 3 INT1 4 Timer 1 6 UART0 7 Timer 2 5 PCA 8 Keyboard 9 TWI 10 SPI 11 UART1 AT89C51RE2 Vector Interrupt Request Address 0000h IE0 0003h TF0 000Bh IE1 0013h IF1 001Bh RI+TI 0023h TF2+EXF2 002Bh CF + CCFn (n = 0-4) 0033h KBDIT 003Bh TWIIT 0043h SPIIT ...
Page 118
... Idle mode is detailed in Table 88. Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 89). The AT89C51RE2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. ...
Page 119
... Entering Power-Down To enter Power-Down mode, set PD bit in PCON register. The AT89C51RE2 enters the Power- Mode Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-Down Mode Note: There are two ways to exit the Power-Down mode: 1. Generate an enabled external interrupt. – ...
Page 120
... Table 88. Pin Conditions in Special Operating Modes Mode Reset Idle (internal code) Idle (external code) Power-Down (internal code) Power-Down (external code) AT89C51RE2 120 Port 0 Port 1 Port 2 Floating High High Data Data Data Floating Data Data Data Data Data Floating Data Data Port 3 ...
Page 121
... Cleared by hardware when an interrupt or reset occurs. PD Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. IDL Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. AT89C51RE2 GF1 GF0 PD 0 IDL ...
Page 122
... CKRL7 Bit Number 7:0 Reset Value = 1111 1111b Not bit addressable Table 91. PCON Register PCON – Power Control Register (87h) 7 SMOD1 Bit Number Reset Value = 00X1 0000b Not bit addressable AT89C51RE2 122 CKRL6 CKRL5 CKRL4 Mnemonic Description Clock Reload Register CKRL ...
Page 123
... CLK PERIPH OSC (X2 Mode) CLK CPU CLK PERIPH OSC and F CLK PERIPH F OSC F = ---------------------------------------------- - × CLKPERIPH 2 255 CKRL – F OSC F = ---------------------------------------------- - × CLKPERIPH 4 255 CKRL – AT89C51RE2 1 CLK Periph 0 CLK CPU Idle CKRL = 0xFF (Standard C51 feature) OSC Peripheral Clock CPU Clock 123 ...
Page 124
... Table 92. WDTRST Register WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C51RE2 124 = 1 make the best use of the WDT, it should be serviced in those sec- CLK PERIPH 7 counter has been added to extend the Time-out capability, = 12MHz ...
Page 125
... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RE2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
Page 126
... Table 94. AUXR Register AUXR - Auxiliary Register (8Eh Bit Number Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable AT89C51RE2 126 XRS2 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...
Page 127
... Keyboard The AT89C51RE2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both Interface high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. The keyboard interface interfaces with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 97), KBE, The Keyboard interrupt Enable register (Table 96), and KBF, the Keyboard Flag register (Table 95) ...
Page 128
... Table 95. KBF Register KBF-Keyboard Flag Register (9Eh) 7 KBF7 Bit Number Reset Value= 0000 0000b AT89C51RE2 128 KBF6 KBF5 KBF4 Bit Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a KBF7 Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. ...
Page 129
... Keyboard line 1 Enable bit KBE1 Cleared to enable standard I/O pin. Set to enable KBF. 1 bit in KBF register to generate an interrupt request. Keyboard line 0 Enable bit KBE0 Cleared to enable standard I/O pin. Set to enable KBF. 0 bit in KBF register to generate an interrupt request. AT89C51RE2 KBE3 KBE2 KBE1 0 ...
Page 130
... Table 97. KBLS Register KBLS-Keyboard Level Selector Register (9Ch) 7 KBLS7 Bit Number Reset Value= 0000 0000b AT89C51RE2 130 KBLS6 KBLS5 KBLS4 Bit Mnemonic Description Keyboard line 7 Level Selection bit KBLS7 Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. ...
Page 131
... Kbit/s in standard mode. Various communication configuration can be designed using this bus. Figure 49 shows a typical 2-wire bus configuration. All the devices connected to the bus can be master and slave. Figure 49. 2-wire Bus Configuration device1 device2 device3 SCL SDA AT89C51RE2 ... deviceN 131 ...
Page 132
... Figure 50. Block Diagram Input Filter SDA PI2.1 Output Stage Input Filter SCL PI2.0 Output Stage AT89C51RE2 132 Address Register SSADR Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status ...
Page 133
... Slave transmitter • Slave receiver Data transfer in each mode of operation is shown in Table to Table 106 and Figure 52. to Figure 55.. These figures contain the following abbreviations START condition R : Read bit (high level at SDA) AT89C51RE2 acknowledgement acknowledgement signal from receiver signal from receiver 1 2 3-8 ...
Page 134
... Master Transmitter Mode Master Receiver Mode AT89C51RE2 134 W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 52 to Figure 55, circles are used to indicate when the serial interrupt flag is set. ...
Page 135
... In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 55). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by AT89C51RE2 ...
Page 136
... Miscellaneous States Notes AT89C51RE2 136 its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS ...
Page 137
... Data 18h A P 20h Other master continues 38h Other master A continues 68h 78h B0h Data A n AT89C51RE2 A P 28h S SLA 10h A P 30h Other master continues 38h To corresponding states in slave mode Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds ...
Page 138
... No SSDAT action Write data byte No SSDAT action Data byte has been 30h transmitted; NOT ACK No SSDAT action has been received No SSDAT action No SSDAT action Arbitration lost in 38h SLA+W or data bytes No SSDAT action AT89C51RE2 138 Application software response To SSCON SSSTA SSSTO SSI SSAA ...
Page 139
... continues 38h Other master A continues 68h 78h B0h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C51RE2 A P Data 58h S SLA R 10h W MT Other master A continues 38h To corresponding states in slave mode ...
Page 140
... Data byte has been 50h received; ACK has been returned Read data byte Read data byte Data byte has been Read data byte 58h received; NOT ACK has been returned Read data byte AT89C51RE2 140 Application software response To SSCON SSSTA SSSTO SSI SSAA ...
Page 141
... SLA W A 60h A 68h General Call A 70h A 78h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C51RE2 Data Data A A 80h 80h 88h Data Data A A 90h 90h A0h ...
Page 142
... Previously addressed with own SLA+W; data has been 88h received; NOT ACK has been returned Previously addressed with general call; data has been 90h received; ACK has been returned AT89C51RE2 142 Application Software Response To/from SSDAT To SSCON STA STO SI No SSDAT action or X ...
Page 143
... No SSDAT action SSDAT action AT89C51RE2 AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if 1 GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA ...
Page 144
... Arbitration lost in SLA+R/W as master; own SLA+R has been B0h received; ACK has been returned Data byte in SSDAT has been B8h transmitted; NOT ACK has been received AT89C51RE2 144 A Data SLA R A8h A B0h Any number of data bytes and their associated Data ...
Page 145
... SI= 0 Bus error due SSDAT 00h illegal START or action STOP condition AT89C51RE2 SI AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if ...
Page 146
... Registers AT89C51RE2 146 Table 107. SSCON Register SSCON - Synchronous Serial Control register (93h CR2 SSIE STA Bit Bit Number Mnemonic Description Control Rate bit 2 7 CR2 See Table 101. Synchronous Serial Interface Enable bit 6 SSIE Clear to disable the TWI module. Set to enable the TWI module. ...
Page 147
... Table 111. SSADR (096h) - Synchronus Serial Address Register (read/write Table 112. SSADR Register - Reset value = FEh Bit Bit Number Mnemonic Description 7 A7 Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit 1 AT89C51RE2 SC1 SC0 147 ...
Page 148
... AT89C51RE2 148 Bit Bit Number Mnemonic Description General Call bit 0 GC Clear to disable the general call address recognition. Set to enable the general call address recognition. 7663D–8051–10/08 ...
Page 149
... The Master may select each Slave device by software through port pins (Figure 57). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. 7663E–8051–10/08 MISO MOSI SCK SS VDD Master Slave 4 Slave 3 AT89C51RE2 Slave 1 Slave 2 149 ...
Page 150
... Table 113. SPI Master Baud Rate Selection SPR2 AT89C51RE2 150 ( Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this mode, the SS is used to start the transmission. SPR1 SPR0 0 ...
Page 151
... MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. 7663E–8051–10/08 Internal Bus MODF SPTE UARTM SPTEIE MODFIE MSTR CPOL CPHA SPR1 SPR0 AT89C51RE2 SPDAT Transmit Data Register Shift Register ...
Page 152
... Figure 60). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device AT89C51RE2 152 8-bit Shift register SPI Clock Generator Master MCU The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Mas- ter SPI should be configured before the Slave SPI ...
Page 153
... MSB bit6 bit5 bit4 bit3 MSB bit6 bit5 bit4 bit3 MSB bit6 bit5 bit4 bit3 bit2 MSB bit6 bit5 bit4 bit3 Byte 1 Byte 2 AT89C51RE2 bit2 bit1 LSB bit2 bit1 LSB 7 8 bit1 LSB bit2 bit1 LSB Byte 3 153 ...
Page 154
... Byte 1 BYTE 1 under transmission SPTE In slave mode it is almost the same except it is the external master that start the transmission. Also, in slave mode new data is ready, the last value received will be the next data byte transmitted. AT89C51RE2 154 B1 MSB B3 B2 LSB ...
Page 155
... MISO z (from slave SPI enable (master (slave) 0 MODF detected When SS is discarded (SS disabled not possible to detect a MODF error in master mode because the SPI is internally unselected and the SS pin is a general purpose I/O. AT89C51RE2 MSB B6 MSB B6 B5 MODF detected 155 ...
Page 156
... Note: While using SPTE interruption for “burst mode” transfers (SPTEIE=’1’), the user soft- ware application should take care to clear SPTEIE, during the last but one data reception (to be able to generate an interrupt on SPIF flag at the end of the last data reception). AT89C51RE2 156 0 ...
Page 157
... Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request . is generated Serial Peripheral Master MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. AT89C51RE2 SPI CPU Interrupt Request CPOL CPHA ...
Page 158
... Table 116. SPSCR Register SPSCR - Serial Peripheral Status and Control register (C4H) 7 SPIF Bit Number AT89C51RE2 158 Bit Mnemonic Description Clock Polarity CPOL Cleared to have the SCK set to’0’ in idle state. Set to have the SCK set to’1’ in idle state. ...
Page 159
... Clear to disable SPTE interrupt generation Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag goes high. To enable SPIF interrupt again, SPTEIE should be cleared. Interrupt Enable for MODF Set and cleared by software: MODFIE - Set to enable MODF interrupt generation - Clear to disable MODF interrupt generation AT89C51RE2 159 ...
Page 160
... However, special care should be taken when writing to them while a transmis- sion is on-going: • Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow. AT89C51RE2 160 7663E–8051–10/08 ...
Page 161
... The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51RE2 is powered up. Description ...
Page 162
... The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. AT89C51RE2 162 t 7663E–8051–10/08 ...
Page 163
... Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. AT89C51RE2 GF1 GF0 PD is still CC 0 ...
Page 164
... The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply con- necting an external capacitor to V characteristics are discussed in the Section “DC Characteristics” of the AT89C51RE2 datasheet. Figure 69. Reset Circuitry and Power-On Reset AT89C51RE2 ...
Page 165
... RST pin. In order to properly propagate this pulse to the rest of the applica- tion in case of external capacitor or power-supply supervisor circuit kΩ resistor must be added as shown Figure 70. Figure 70. Recommended Reset Output Schematic 7663E–8051–10/08 VDD + RST VDD 1K RST VSS AT89C51RE2 To other on-board circuitry 165 ...
Page 166
... Input High Voltage RST, XTAL1 IH1 V Output Low Voltage, ports Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports Output High Voltage, port 0, ALE, PSEN OH1 AT89C51RE2 166 Note: + 0.5V CC (2) =2.7V to 5.5V MHz Min Typ -0.5 0 0.9 CC 0.7 V ...
Page 167
... Pins are not guaranteed to sink current greater OL Test Condition, Active Mode RST EA XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS AT89C51RE2 Max Unit k Ω (5) 250 μ A -50 ± 10 μ A μ A -650 10 pF μ A 150 0.4 x Frequency (MHz 0.3 x Frequency (MHz 0.8 x Frequency (MHz ...
Page 168
... Table 120, Table 121 and Table 127 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. Take the x value in the corre- sponding column (-M or -L) and use this value in the formula. AT89C51RE2 168 Test Condition, Idle Mode ...
Page 169
... Address to Valid Instruction In AVIV T PSEN Low to Address Float PLAZ (1) -M Min Max LHLL 5 AVLL 5 LLAX n 65 LLIV 5 LLPL 50 PLPH 30 PLIV 0 PXIX 10 PXIZ 80 AVIV 10 PLAZ 1. ‘ -L ‘ refers 5.5V version. 2. ‘ -M ’ refers to 4.5V to 5.5V version. AT89C51RE2 (2) -L Units Min Max 169 ...
Page 170
... Table 121. AC Parameters for a Variable Clock Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ Notes: AT89C51RE2 170 Standard Type Clock X2 Clock Min Min 0 Min 0 Max Min 0 Min 1 Max 1 Min x Max 0 Max 2 Max x 1. ‘ -L ‘ refers 5.5V version. ...
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... ALE to Valid Data In LLDV T Address to Valid Data In AVDV T ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data Set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C51RE2 CLCL T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 171 ...
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... Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Notes: AT89C51RE2 172 (1) -M Min 125 125 155 ‘ -L ‘ refers 5.5V version. 2. ‘ -M ’ refers to 4.5V to 5.5V version. (2) -L Max Min Max 125 125 155 ...
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... Max Max 4 Min 1 Max 1 Min Min 0 Min 3 Min 0 Max x x Min 0 Max 0 ‘ -L ‘ refers 5.5V version. 2. ‘ -M ’ refers to 4.5V to 5.5V version. T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 AT89C51RE2 X parameter for X parameter for (1) (2) -M range -L range WHLH T WLWH ...
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... OR SFR-P2 Serial Port Timing - Table 125. Symbol Description Shift Register Mode Symbol Table 126. AC Parameters for a Fix Clock Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Notes: AT89C51RE2 174 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Parameter T Serial port clock cycle time ...
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... T XHDX T XHDV VALID VALID VALID V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC 0.45V CC min. for a logic “1” and 0. 0.1V OL AT89C51RE2 X Parameter For X Parameter For (1) (2) -M Range -L Range 133 133 SET TI VALID VALID VALID VALID SET RI T CHCX T T CLCX ...
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... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51RE2 176 STATE5 STATE6 ...
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... FBUSY flag Parameter Input PSEN# Valid to RST Edge Input PSEN# Hold after RST Edge Flash Internal Busy (Programming) Time Number of Flash Erase/Write Cycles Flash Retention Time RST T SVRL PSEN#1 FBUSY bit AT89C51RE2 Conditions L Low V Valid X No Longer Valid Min Typ Max 50 ...
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... Ordering Information Table 130. Possible Order Entries AT89C51RE2 178 Part Number Supply Voltage AT89C51RE2-SLSUM 2.7V-5.5V AT89C51RE2-RLTUM AT89C51RE2-SLSEM 2.7V-5.5V AT89C51RE2-RLTEM Temperature Range Package PLCC44 Industrial & Green VQFP44 PLCC44 Engineering Samples VQFP44 7663E–8051–10/08 ...
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... Packaging Information PLCC44 7663E–8051–10/08 AT89C51RE2 179 ...
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... STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE. AT89C51RE2 180 7663E–8051–10/08 ...
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... VQFP44 7663E–8051–10/08 AT89C51RE2 181 ...
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... DATUM "A" AND "D" DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. AT89C51RE2 182 7663E–8051–10/08 ...
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... History Changes from 1. Modified ordering information. 7663B to 7663C 2. Various grammatical corections throughout document. Changes from 1. TWI interface added. 7663C to 7663D Changes from 1. Removed 64 and 68 pins package product version. 7663D to 7663E 2. Minor correction on Table 69 on page 102. 7663E–8051–10/08 AT89C51RE2 183 ...
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... On-Chip ROM bootloader ................................................................................... 31 Boot process....................................................................................................... 32 Access and Operations Descriptions.................................................................. 36 Operation Cross Memory Access ..................................................... 50 Sharing Instructions ........................................................................... 50 Flash Protection from Parallel Programming .................................. 52 Bootloader Architecture .................................................................... 53 Introduction ......................................................................................................... 53 Bootloader Description ....................................................................................... 54 ISP Protocol Description..................................................................................... 56 Protocol............................................................................................................... 57 ISP Commands description ................................................................................ 61 Timers/Counters ................................................................................. 68 Timer/Counter Operations .................................................................................. 68 Timer 0................................................................................................................ 68 Timer 1................................................................................................................ 71 AT89C51RE2 1 7663E–8051–10/08 ...
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... Power-Down Mode ........................................................................................... 118 Registers........................................................................................................... 121 Oscillator ........................................................................................... 122 Registers........................................................................................................... 122 Functional Block Diagram .................................................................................123 Hardware Watchdog Timer .............................................................. 124 Using the WDT ................................................................................................. 124 WDT During Power Down and Idle................................................................... 125 Reduced EMI Mode ........................................................................... 126 Keyboard Interface ........................................................................... 127 Registers........................................................................................................... 128 7663E–8051–10/08 AT89C51RE2 2 ...
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... Absolute Maximum Ratings ..............................................................................166 DC Parameters .................................................................................................166 AC Parameters ................................................................................................. 168 Ordering Information ........................................................................ 178 Packaging Information ..................................................................... 179 PLCC44 ............................................................................................................ 179 VQFP44 ............................................................................................................ 181 Document Revision History ............................................................. 183 Changes from 7663B to 7663C ........................................................................ 183 Changes from 7663C to 7663D ........................................................................ 183 Changes from 7663D to 7663E ........................................................................ 183 AT89C51RE2 3 7663E–8051–10/08 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...