ATMEGA329P-20AU Atmel, ATMEGA329P-20AU Datasheet
ATMEGA329P-20AU
Specifications of ATMEGA329P-20AU
ATMEGA329P-16AU
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ATMEGA329P-20AU Summary of contents
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... Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Segment LCD Driver (ATmega329P) – Segment LCD Driver (ATmega3290P) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – ...
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... Pin Configurations Figure 1-1. MLF/ Pinout ATmega329P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol- dered or glued to the board to ensure good mechanical stability ...
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... DNC 18 DNC 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 22 (MISO/PCINT11) PB3 23 (OC0A/PCINT12) PB4 24 (OC1A/PCINT13) PB5 25 (OC1B/PCINT14) PB6 8021GS–AVR–03/11 INDEX CORNER ATmega329P/3290P 75 PA3 (COM3) 74 PA4 (SEG0) 73 PA5 (SEG1) 72 PA6 (SEG2) 71 PA7 (SEG3) 70 PG2 (SEG4) 69 PC7 (SEG5) 68 PC6 (SEG6) 67 DNC 66 PH3 (PCINT19/SEG7) ...
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... Overview The ATmega329P/3290P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329P/3290P achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Self-Programmable Flash on a monolithic chip, the Atmel ATmega329P/3290P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded con- trol applications. The ATmega329P/3290P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega329P/3290P as listed on page 8021GS– ...
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... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega329P/3290P as listed on page 2 ...
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... V 8021GS–AVR–03/11 336. Shorter pulses are not guaranteed to generate a reset. , even if the ADC is not used. If the ADC is used, it should be connected large capacitance reduces ripple on V LCD reaches its target value. LCD ATmega329P/3290P ”System and Reset but increases LCD CC Fig- 8 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 8021GS–AVR–03/11 1. ATmega329P/3290P 9 ...
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... USART0 Data Register ATmega329P/3290P Bit 3 Bit 2 Bit 1 SEG335 SEG334 SEG333 SEG327 SEG326 SEG325 SEG319 SEG318 SEG317 SEG311 SEG310 SEG309 SEG303 SEG302 SEG301 SEG235 SEG234 SEG233 SEG227 SEG226 SEG225 SEG219 ...
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... Timer/Counter1 Output Compare Register B High Timer/Counter1 Output Compare Register B Low Timer/Counter1 Output Compare Register A High Timer/Counter1 Output Compare Register A Low Timer/Counter1 Input Capture Register High Timer/Counter1 Input Capture Register Low ATmega329P/3290P Bit 3 Bit 2 Bit USBS0 UCSZ01 UCSZ00 UCPOL0 TXEN0 ...
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... OCDR6 OCDR5 OCDR4 ACBG ACO ACI - - - SPI Data Register WCOL - - SPE DORD MSTR General Purpose I/O Register General Purpose I/O Register - - - - - - Timer/Counter0 Output Compare A ATmega329P/3290P Bit 3 Bit 2 Bit WGM12 CS12 CS11 - - WGM11 - - AIN1D ADC3D ADC2D ADC1D - - - MUX3 MUX2 MUX1 - ...
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... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega329P/3290P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega329P/3290P Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...
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... Rr, Y ← ← (Y) ← ← Rr (Z) ← Rr (Z) ← Rr, Z ← ← (Z) ← ← Rr (k) ← ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← ← Rr ATmega329P/3290P Operation Flags #Clocks None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V ...
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... No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8021GS–AVR–03/11 Description STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega329P/3290P Operation Flags #Clocks None None None None None None ...
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... Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 8021GS–AVR–03/11 (2) Ordering Code ATmega329PV-10AU 64A (4) ATmega329PV-10AUR 64A ATmega329PV-10MU 64M1 (4) ATmega329PV-10MUR 64M1 ATmega329P-20AU 64A (4) ATmega329P-20AUR 64A ATmega329P-20MU 64M1 (4) ATmega329P-20MUR 64M1 ATmega329P-AN 64A (4) ATmega329P-ANR 64A ATmega329P-MN 64M1 (4) ATmega329P-MNR 64M1 and Figure 28-3 on page ...
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... Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 8021GS–AVR–03/11 (2) Ordering Code ATmega3290PV-10AU (4) ATmega3290PV-10AUR ATmega3290P-20AU (4) ATmega3290P-20AUR ATmega3290P-AN 64A (4) ATmega3290P-ANR 64A ATmega3290P-MN 64M1 (4) ATmega3290P-MNR 64M1 and Figure 28-3 on page Package Type ATmega329P/3290P (1) Package Type Operational Range Industrial 100A 0°C to 85°C) (-4 Extended 0°C to 105°C) (-4 334. (5) 18 ...
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... San Jose, CA 95131 R 8021GS–AVR–03/11 B PIN 1 IDENTIFIER TITLE 64A, 64-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega329P/3290P A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A – – 1.20 A1 0.05 – ...
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... Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega329P/3290P C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A 0 ...
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... Orchard Parkway San Jose, CA 95131 R 8021GS–AVR–03/11 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega329P/3290P A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOTE SYMBOL NOM A – – 1.20 A1 0.05 – ...
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... Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 10.3 ATmega329P rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00 ...
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... Timer/Counter register (TCNTx) is 0x00. Problem Fix/ Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 8021GS–AVR–03/11 ATmega329P/3290P 23 ...
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... Table 8-6 on page 30, Capacitance for Low-frequency Oscillator. Updated the document with Atmel new style guide included “Atmel blue logo”. Updated Figure 29-11 on page 356 Added Typical chara for ”ATmega329P” on page ”ATmega649P” on page 443, and updated. Updated ”Ordering Information” on page Updated ” ...
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... Port A Data Register” on page Bullet five updated in ”Asynchronous Operation of Timer/Counter2” on page 152. Updated ”System and Reset Characteristics” on page Added errata for ”ATmega329P rev. C” on page 416 C” on page 417. Updated.”Errata” on page 416. Updated ”Features” on page 1 ...
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