DSPIC33FJ128MC708A-I/PT

Manufacturer Part NumberDSPIC33FJ128MC708A-I/PT
DescriptionIC DSPIC MCU/DSP 128K 80-TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128MC708A-I/PT datasheet
 

Specifications of DSPIC33FJ128MC708A-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case80-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o69Ram Size16K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 18x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os69
Data Ram Size16 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Package80TQFPDevice CoredsPIC
Family NamedsPIC33Maximum Speed40 MHz
Operating Supply Voltage3.3 VInterface TypeCAN/I2C/SPI/UART
On-chip Adc36-chx10-bit|36-chx12-bitNumber Of Timers9
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size-  
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dsPIC33FJXXXMCX06A/X08A/X10A
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
Preliminary
 2009 Microchip Technology Inc.
DS70594B

DSPIC33FJ128MC708A-I/PT Summary of contents

  • Page 1

    ... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70594B ...

  • Page 2

    ... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... available interrupt sources • five external interrupts • Seven programmable priority levels • Five processor exceptions  2009 Microchip Technology Inc. dsPIC33FJXXXMCX06A/X08A/X10A Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change pins • Output pins can drive from 3.0V to 3.6V • ...

  • Page 4

    ... Industrial and extended temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 80-pin TQFP (12x12x1 mm) • 64-pin TQFP (10x10x1 mm) • 64-pin QFN (9x9x0.9 mm) Note: See the device variant tables for exact peripheral features per device. Preliminary  2009 Microchip Technology Inc. ...

  • Page 5

    ... Note 1: RAM size is inclusive of 2 Kbytes DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions.  2009 Microchip Technology Inc. ...

  • Page 6

    ... Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to V externally. SS DS70594B-page dsPIC33FJ128MC506A dsPIC33FJ64MC506A dsPIC33FJ128MC706A dsPIC33FJ64MC706A Preliminary = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/FLTB/INT2/RD9 42 IC1/FLTA/INT1/RD8 OSC2/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3  2009 Microchip Technology Inc. ...

  • Page 7

    ... PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/CN4/RB2 14 15 PGEC3/AN1/V -/CN3/RB1 REF PGED3/AN0/V +/CN2/RB0 16 REF  2009 Microchip Technology Inc dsPIC33FJ128MC506A 41 dsPIC33FJ64MC506A 40 dsPIC33FJ128MC706A 39 dsPIC33FJ64MC706A Preliminary = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD ...

  • Page 8

    ... SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGEC3/AN1/CN3/RB1 19 PGED3/AN0/CN2/RB0 20 DS70594B-page 8 dsPIC33FJ64MC508A Preliminary = Pins are tolerant 60 PGEC2/SOSCO/T1CK/CN0/RC14 59 PGED2/SOSCI/CN1/RC13 58 OC1/RD0 57 IC4/RD11 56 IC3/RD10 55 IC2/RD9 54 IC1/RD8 53 SDA2/INT4/RA3 52 SCL2/INT3/RA2 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 46 SDA1/RG3 45 SCK1/INT0/RF6 SDI1/RF7 44 SDO1/RF8 43 42 U1RX/RF2 41 U1TX/RF3  2009 Microchip Technology Inc. ...

  • Page 9

    ... AN16/T2CK/T7CK/RC1 4 AN17/T3CK/T6CK/RC2 5 SCK2/CN8/RG6 6 7 SDI2/CN9/RG7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGEC3/AN1/CN3/RB1 19 PGED3/AN0/CN2/RB0 20  2009 Microchip Technology Inc. dsPIC33FJ128MC708A Preliminary = Pins are tolerant 60 PGEC2/SOSCO/T1CK/CN0/RC14 59 PGED2/SOSCI/CN1/RC13 58 OC1/RD0 57 IC4/RD11 IC3/RD10 56 IC2/RD9 55 54 IC1/RD8 53 SDA2/INT4/RA3 52 SCL2/INT3/RA2 OSC2/CLKO/RC15 50 OSC1/CLKIN/RC12 SCL1/RG2 46 SDA1/RG3 SCK1/INT0/RF6 45 ...

  • Page 10

    ... AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 DS70594B-page 10 dsPIC33FJ64MC510A Preliminary = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 61 60 TDI/RA4 59 SDA2/RA3 SCL2/RA2 58 57 SCL1/RG2 56 SDA1/RG3 SCK1/INT0/RF6 55 SDI1/RF7 54 SDO1/RF8 53 U1RX/RF2 52 51 U1TX/RF3  2009 Microchip Technology Inc. ...

  • Page 11

    ... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25  2009 Microchip Technology Inc. dsPIC33FJ128MC510A dsPIC33FJ256MC510A Preliminary = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 ...

  • Page 12

    ... AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 25 PGED3/AN0/CN2/RB0 DS70594B-page 12 dsPIC33FJ64MC710A dsPIC33FJ128MC710A dsPIC33FJ256MC710A Preliminary = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 IC1/RD8 68 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 64 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 59 SDA2/RA3 SCL2/RA2 58 57 SCL1/RG2 56 SDA1/RG3 55 SCK1/INT0/RF6 54 SDI1/RF7 53 SDO1/RF8 52 U1RX/RF2 51 U1TX/RF3  2009 Microchip Technology Inc. ...

  • Page 13

    ... Appendix A: Migrating from dsPIC33FJXXXMCX06/X08/X10 Devices to dsPIC33FJXXXMCX06A/X08A/X10A Devices ............... 341 Appendix B: Revision History............................................................................................................................................................. 342 Index ................................................................................................................................................................................................. 343 The Microchip Web Site ..................................................................................................................................................................... 349 Customer Change Notification Service .............................................................................................................................................. 349 Customer Support .............................................................................................................................................................................. 349 Reader Response .............................................................................................................................................................................. 350 Product Identification System ............................................................................................................................................................ 351  2009 Microchip Technology Inc. Preliminary DS70594B-page 13 ...

  • Page 14

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70594B-page 14 Preliminary  2009 Microchip Technology Inc. ...

  • Page 15

    ... The dsPIC33FJXXXMCX06A/X08A/X10A devices with a wide range of pin counts (64, 80 and 100), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes, 16 Kbytes and 30 Kbytes).  ...

  • Page 16

    ... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-Bit ALU MCLR Timers ADC1,2 QEI 1-9 CN1-23 SPI1,2 I2C1,2 Preliminary PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 PORTF 16 PORTG 16 ECAN1,2 UART1,2  2009 Microchip Technology Inc. ...

  • Page 17

    ... OSC2 I/O — Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels  2009 Microchip Technology Inc. Description Analog input channels. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...

  • Page 18

    ... UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Analog = Analog input O = Output Preliminary P = Power I = Input  2009 Microchip Technology Inc. ...

  • Page 19

    ... I Analog REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels  2009 Microchip Technology Inc. Description Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input ...

  • Page 20

    ... NOTES: DS70594B-page 20 Preliminary  2009 Microchip Technology Inc. ...

  • Page 21

    ... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source.  2009 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...

  • Page 22

    ... MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R1 MCLR dsPIC33F C and V specifications are met and V specifications are met. IL  2009 Microchip Technology Inc. ...

  • Page 23

    ... Guide” (DS51616) ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) (DS51749)  2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” ...

  • Page 24

    ... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. Preliminary  2009 Microchip Technology Inc ...

  • Page 25

    ... Figure 3-2.  2009 Microchip Technology Inc. 3.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes, and is split into two blocks referred and Y data memory. Each memory block has its own independent Address Generation Unit (AGU) ...

  • Page 26

    ... PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary devices DMA 16 RAM DMA Controller 16-Bit ALU 16 To Peripheral Modules  2009 Microchip Technology Inc. ...

  • Page 27

    ... Registers AD39 DSP AccA Accumulators AccB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH  2009 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 ...

  • Page 28

    ... This bit may be read or cleared (not set). Clearing this bit will clear SA and SB. DS70594B-page 28 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) (4) Preliminary R/C R/W-0 (4) SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0  2009 Microchip Technology Inc. ...

  • Page 29

    ... The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). 4: This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.  2009 Microchip Technology Inc. (2) Preliminary DS70594B-page 29 ...

  • Page 30

    ... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70594B-page 30 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set  2009 Microchip Technology Inc. ...

  • Page 31

    ... W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algo- rithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same num- ber of cycles to execute.  2009 Microchip Technology Inc. 3.6 DSP Engine ALU is ...

  • Page 32

    ... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70594B-page 32 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill  2009 Microchip Technology Inc. ...

  • Page 33

    ... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation.  2009 Microchip Technology Inc. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true, or complement data into the other input ...

  • Page 34

    ... Section 3.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary to data saturation (see  2009 Microchip Technology Inc. ...

  • Page 35

    ... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.  2009 Microchip Technology Inc. 3.6.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

  • Page 36

    ... NOTES: DS70594B-page 36 Preliminary  2009 Microchip Technology Inc. ...

  • Page 37

    ... Reserved Device Configuration Registers Reserved DEVID (2) Note: Memory areas are not shown to scale.  2009 Microchip Technology Inc. 4.1 Program Address Space The program address dsPIC33FJXXXMCX06A/X08A/X10A devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4 ...

  • Page 38

    ... A more detailed discussion of the interrupt vec- tor tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary devices addresses between 0x00000 and devices also PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006  2009 Microchip Technology Inc. ...

  • Page 39

    ... Data byte writes only write to the corresponding side of the array or register which matches the byte address.  2009 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations or translating from 8-bit MCU code ...

  • Page 40

    ... Program Memory 0xFFFF DS70594B-page 40 LSb 16 Bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8-Kbyte Near Data Space  2009 Microchip Technology Inc. ...

  • Page 41

    ... SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 0x8001 Optionally Mapped into Program Memory 0xFFFF  2009 Microchip Technology Inc. LSb Address 16 Bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE ...

  • Page 42

    ... Mapped into Program Memory 0xFFFF DS70594B-page 42 LSb Address 16 Bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x47FE 0x4800 Y Data RAM (Y) 0x77FE 0x7800 DMA RAM 0x7FFE 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary  2009 Microchip Technology Inc. 8-Kbyte Near Data Space ...

  • Page 43

    ... All Effective Addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device.  2009 Microchip Technology Inc. 4.2.6 DMA RAM Every dsPIC33FJXXXMCX06A/X08A/X10A contains 2 Kbytes of dual ported DMA RAM located at the end of Y data space ...

  • Page 44

    TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

  • Page 45

    TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — BSRAM 0750 — — — SSRAM 0752 — — — Legend: x ...

  • Page 46

    TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX10A DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE ...

  • Page 47

    TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 ...

  • Page 48

    TABLE 4-6: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

  • Page 49

    TABLE 4-7: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...

  • Page 50

    TABLE 4-8: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

  • Page 51

    TABLE 4-9: 8-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...

  • Page 52

    TABLE 4-10: QEI REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name . QEI1CON 01E0 CNTERR — QEISIDL INDX UPDN DFLT1CON 01E2 — — — — — POS1CNT 01E4 MAX1CNT 01E6 Legend ...

  • Page 53

    TABLE 4-13: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...

  • Page 54

    TABLE 4-17: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...

  • Page 55

    TABLE 4-19: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

  • Page 56

    TABLE 4-19: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...

  • Page 57

    TABLE 4-20: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — — — C1FCTRL ...

  • Page 58

    TABLE 4-22: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 SID<10:3> C1RXM0EID 0432 ...

  • Page 59

    TABLE 4-22: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> ...

  • Page 60

    TABLE 4-23: ECAN2 REGISTER MAP WHEN WIN (C1CTRL<0> FOR dsPIC33FJXXXMC708A/710A DEVICES File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL ...

  • Page 61

    TABLE 4-25: ECAN2 REGISTER MAP WHEN WIN (C1CTRL<0> FOR dsPIC33FJXXXMC708A/710A DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500- 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F11BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID 0530 ...

  • Page 62

    TABLE 4-25: ECAN2 REGISTER MAP WHEN WIN (C1CTRL<0> FOR dsPIC33FJXXXMC708A/710A DEVICES (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF11SID 056C C2RXF11EID 056E EID<15:8> C2RXF12SID 0570 C2RXF12EID 0572 EID<15:8> C2RXF13SID 0574 C2RXF13EID 0576 EID<15:8> ...

  • Page 63

    TABLE 4-28: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 PORTC 02CE RC15 RC14 RC13 RC12 LATC 02D0 LATC15 LATC14 LATC13 LATC12 Legend unknown value ...

  • Page 64

    TABLE 4-32: PORTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02E6 RG15 RG14 RG13 RG12 LATG 02E8 LATG15 LATG14 LATG13 LATG12 ODCG 06E4 ODCG15 ODCG14 ODCG13 ...

  • Page 65

    ... W15 (before CALL) PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++]  2009 Microchip Technology Inc. 4.2.8 DATA RAM PROTECTION FEATURE The dsPIC33FJXXXMCX06A/X08A/X10A support data RAM protection features which enable segments of RAM to be protected when used in con- junction with Boot and Secure Code Segment Security. ...

  • Page 66

    ... Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. Preliminary  2009 Microchip Technology Inc. ...

  • Page 67

    ... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 Words  2009 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...

  • Page 68

    ... BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that using has been designated as the Bit-Reversed Pointer. Preliminary N bytes, should not be enabled Modulo Addressing will be  2009 Microchip Technology Inc. ...

  • Page 69

    ... TABLE 4-37: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address  2009 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal ...

  • Page 70

    ... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx Preliminary  2009 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...

  • Page 71

    ... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.  2009 Microchip Technology Inc. Program Counter 0 23 Bits ...

  • Page 72

    ... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area. Preliminary  2009 Microchip Technology Inc. ...

  • Page 73

    ... PAG is mapped into the upper half of the data memory space...  2009 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...

  • Page 74

    ... NOTES: DS70594B-page 74 Preliminary  2009 Microchip Technology Inc. ...

  • Page 75

    ... Using 1/0 Table Instruction User/Configuration Space Select  2009 Microchip Technology Inc. Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed ...

  • Page 76

    ... PROGRAMMING TIME T %   % FRC Accuracy FRC Tuning 11064 Cycles =       0.05 1 0.00375 – 11064 Cycles =       – – 1 0.05 1 0.00375  2009 Microchip Technology Inc. ...

  • Page 77

    ... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented.  2009 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 ...

  • Page 78

    ... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary  2009 Microchip Technology Inc. ...

  • Page 79

    ... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP  2009 Microchip Technology Inc Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...

  • Page 80

    ... NOTES: DS70594B-page 80 Preliminary  2009 Microchip Technology Inc. ...

  • Page 81

    ... V DD Trap Conflict Illegal Opcode Uninitialized W Register  2009 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure 6-1. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...

  • Page 82

    ... DS70594B-page 82 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (2) Preliminary U-0 R/W-0 (3) — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 83

    ... All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: For dsPIC33FJ256MCX06A/X08A/X10A devices, this bit is unimplemented and reads back a programmed value.  2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary DS70594B-page 83 ...

  • Page 84

    ... The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. Preliminary Clearing Event POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, POR, BOR POR, BOR POR, BOR — —  2009 Microchip Technology Inc. ...

  • Page 85

    ... Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the OST oscillator clock to the system. = PLL lock time (20 s nominal LOCK = Fail-Safe Clock Monitor delay (100 s nominal FSCM  2009 Microchip Technology Inc. System Clock SYSRST Delay Delay — POR STARTUP RST ...

  • Page 86

    ... Reset value for the Reset Control register, RCON, depends on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. Preliminary  2009 Microchip Technology Inc FSCM ...

  • Page 87

    ... The dsPIC33FJXXXMCX06A/X08A/X10A family of devices implement unique interrupts and five nonmaskable traps. These are summarized in Table 7-1 and Table 7-2.  2009 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1 ...

  • Page 88

    ... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70594B-page 88 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1)  2009 Microchip Technology Inc. ...

  • Page 89

    ... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...

  • Page 90

    ... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved  2009 Microchip Technology Inc. ...

  • Page 91

    ... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.  2009 Microchip Technology Inc. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

  • Page 92

    ... R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C-0 R-0 R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set  2009 Microchip Technology Inc. ...

  • Page 93

    ... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

  • Page 94

    ... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70594B-page 94 Preliminary  2009 Microchip Technology Inc. ...

  • Page 95

    ... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

  • Page 96

    ... Interrupt request has not occurred DS70594B-page 96 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA01IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 97

    ... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. Preliminary DS70594B-page 97 ...

  • Page 98

    ... Interrupt request has not occurred DS70594B-page 98 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IF DMA21IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 99

    ... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. Preliminary DS70594B-page 99 ...

  • Page 100

    ... DS70594B-page 100 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF R/W-0 R/W-0 R/W-0 DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 101

    ... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. Preliminary DS70594B-page 101 ...

  • Page 102

    ... DS70594B-page 102 U-0 U-0 R/W-0 — — QEIIF R/W-0 R/W-0 R/W-0 T9IF T8IF MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PWMIF C2IF bit 8 R/W-0 R/W-0 SI2C2IF T7IF bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 103

    ... SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. Preliminary DS70594B-page 103 ...

  • Page 104

    ... DS70594B-page 104 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IF — U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 U1EIF FLTBIF bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 105

    ... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...

  • Page 106

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594B-page 106 Preliminary  2009 Microchip Technology Inc. ...

  • Page 107

    ... AD2IE: ADC2 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 ...

  • Page 108

    ... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594B-page 108 Preliminary  2009 Microchip Technology Inc. ...

  • Page 109

    ... DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...

  • Page 110

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594B-page 110 Preliminary  2009 Microchip Technology Inc. ...

  • Page 111

    ... T8IE: Timer8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEIIE R/W-0 R/W-0 ...

  • Page 112

    ... IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 (CONTINUED) bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70594B-page 112 Preliminary  2009 Microchip Technology Inc. ...

  • Page 113

    ... U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 FLTBIE: PWM Fault B Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...

  • Page 114

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 115

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 116

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 117

    ... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

  • Page 118

    ... Interrupt source is disabled DS70594B-page 118 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 119

    ... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 120

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 121

    ... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 122

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 122 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 123

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 124

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 124 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 IC6IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 125

    ... Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...

  • Page 126

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 126 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 T7IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 127

    ... Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 128

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 128 R/W-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 QEIIP<2:0> bit 8 R/W-0 R/W-0 C2IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 129

    ... DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — ...

  • Page 130

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70594B-page 130 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2EIP<2:0> bit 8 R/W-0 R/W-0 FLTBIP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 131

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 132

    ... Interrupt vector pending is number 9 0000000 = Interrupt vector pending is number 8 DS70594B-page 132 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 133

    ... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2009 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...

  • Page 134

    ... NOTES: DS70594B-page 134 Preliminary  2009 Microchip Technology Inc. ...

  • Page 135

    ... CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. The dsPIC33FJXXXMCX06A/X08A/X10A peripherals that can utilize DMA are listed in Table 8-1 along with their associated Interrupt Request (IRQ) numbers.  2009 Microchip Technology Inc. TABLE 8-1: PERIPHERALS WITH DMA SUPPORT Peripheral INT0 ...

  • Page 136

    ... Note: For clarity, CPU and DMA address buses are not shown. DS70594B-page 136 Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus Preliminary DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1  2009 Microchip Technology Inc. ...

  • Page 137

    ... One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled  2009 Microchip Technology Inc. • A 16-Bit DMA RAM Secondary Start Address Offset register (DMAxSTB) • A 16-Bit DMA Peripheral Address register (DMAxPAD) • ...

  • Page 138

    ... U-0 U-0 — — R/W-0 U-0 U-0 (2) (2) (2) IRQSEL4 IRQSEL3 IRQSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) (2) (2) IRQSEL1 IRQSEL0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 139

    ... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 140

    ... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 141

    ... XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected  2009 Microchip Technology Inc. R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 ...

  • Page 142

    ... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected DS70594B-page 142 Preliminary  2009 Microchip Technology Inc. ...

  • Page 143

    ... PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected  2009 Microchip Technology Inc. U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 ...

  • Page 144

    ... DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70594B-page 144 R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 145

    ... SOSCI Note 1: See Figure 9-2 for PLL details the Oscillator is used with modes, an extended parallel resistor with the value of 1 M must be connected.  2009 Microchip Technology Inc. The dsPIC33FJXXXMCX06A/X08A/X10A oscillator system provides the following: • Various external and internal oscillator options as clock sources • ...

  • Page 146

    ... MIPS. For a primary oscillator or FRC oscillator output, ‘F the PLL output, ‘F ’, is given by the following OSC equation: EQUATION 9-2: F OSC OSC bits, Preliminary  2009 Microchip Technology Inc divided OSC ) and the defines the OSC = ------------- 2 selected ...

  • Page 147

    ... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device.  2009 Microchip Technology Inc. EQUATION 9-3: F OSC F = ------------- CY 2 ...

  • Page 148

    ... PLL modes. DS70594B-page 148 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary  2009 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...

  • Page 149

    ... Direct clock switches between any primary oscillator mode with PLL and FRCPLL modes are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2009 Microchip Technology Inc. (1) (CONTINUED) ...

  • Page 150

    ... This bit is cleared when the ROI bit is set and an interrupt occurs. DS70594B-page 150 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 151

    ... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 152

    ... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70594B-page 152 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 153

    ... NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted.  2009 Microchip Technology Inc valid clock switch has been initiated, the LOCK (OSCCON<3>) status bits are cleared. ...

  • Page 154

    ... NOTES: DS70594B-page 154 Preliminary  2009 Microchip Technology Inc. ...

  • Page 155

    ... EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2009 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes dsPIC33FJXXXMCX06A/X08A/X10A two special power-saving modes that are entered through the execution of a special PWRSAV instruction. ...

  • Page 156

    ... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC variant. If the  2009 Microchip Technology Inc. ...

  • Page 157

    ... SPI2 module is disabled 0 = SPI2 module is enabled Note 1: The PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode.  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T2MD T1MD ...

  • Page 158

    ... AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: The PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode. DS70594B-page 158 (1) Preliminary  2009 Microchip Technology Inc. ...

  • Page 159

    ... OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 IC5MD IC4MD IC3MD R/W-0 ...

  • Page 160

    ... Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70594B-page 160 Preliminary  2009 Microchip Technology Inc. ...

  • Page 161

    ... AD2 module is disabled 0 = AD2 module is enabled Note 1: The PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode.  2009 Microchip Technology Inc. R/W-0 U-0 U-0 T6MD — ...

  • Page 162

    ... NOTES: DS70594B-page 162 Preliminary  2009 Microchip Technology Inc. ...

  • Page 163

    ... CK Data Latch Read LAT Read Port  2009 Microchip Technology Inc. also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected ...

  • Page 164

    ... Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. ; Configure PORTB<15:8> as inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction Preliminary capable of detecting input  2009 Microchip Technology Inc. ...

  • Page 165

    ... SOSCI TGATE 1 Set T1IF 0 Reset Equal  2009 Microchip Technology Inc. Timer1 also supports the following features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling ...

  • Page 166

    ... Unimplemented: Read as ‘0’ DS70594B-page 166 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 167

    ... For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers.  2009 Microchip Technology Inc. Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are ignored. Only T2CON, T4CON, T6CON and T8CON control bits are used for setup and control ...

  • Page 168

    ... The 32-Bit Timer Control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respec- tive to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70594B-page 168 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync  2009 Microchip Technology Inc. ...

  • Page 169

    ... FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal  2009 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70594B-page 169 ...

  • Page 170

    ... The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins. DS70594B-page 170 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (1) — TCS — bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 171

    ... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.  2009 Microchip Technology Inc. U-0 U-0 (2) — ...

  • Page 172

    ... NOTES: DS70594B-page 172 Preliminary  2009 Microchip Technology Inc. ...

  • Page 173

    ... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel.  2009 Microchip Technology Inc. - Capture timer value on every rising edge of input at ICx pin 2. Capture timer value on every edge (rising and falling) of input at ICx pin 3 ...

  • Page 174

    ... Timer selections may vary. Refer to the device data sheet for details. DS70594B-page 174 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 175

    ... An ‘x’ signal, register or bit name denotes the number of the output compare channels. 2: The OCFA pin controls OC1 through OC4. The OCFB pin controls OC5 through OC8.  2009 Microchip Technology Inc. The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected ...

  • Page 176

    ... OCx rising and falling edge OCx falling edge 0 OCx falling edge 0 ‘0’ if OCxR is zero, No interrupt ‘1’ if OCxR is non-zero ‘0’ if OCxR is zero, OCFA falling edge for OC1 to OC4 ‘1’ if OCxR is non-zero Timer is Reset on Period Match Preliminary  2009 Microchip Technology Inc. — ...

  • Page 177

    ... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled  2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 178

    ... NOTES: DS70594B-page 178 Preliminary  2009 Microchip Technology Inc. ...

  • Page 179

    ... AC Induction Motor • Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS)  2009 Microchip Technology Inc. The PWM module has the following features: • Eight PWM I/O pins with four duty cycle generators • 16-bit resolution • ...

  • Page 180

    ... Channel 2 Dead-Time Generator 2 Generator and Override Logic PWM Channel 1 Dead-Time Generator 1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM4H PWM4L PWM3H Output PWM3L Driver PWM2H Block PWM2L PWM1H PWM1L FLTA FLTB Special Event Trigger  2009 Microchip Technology Inc. ...

  • Page 181

    ... PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in a Single Pulse mode 00 = PWM time base operates in a Free-Running mode  2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 182

    ... Bit is cleared R/W-0 R/W-0 R/W-0 PTPER<14:8> R/W-0 R/W-0 R/W-0 PTPER<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 183

    ... A Special Event Trigger will occur when the PWM time base is counting upwards bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits Note 1: SEVTDIR is compared with PTDIR (PTMR<15>) to generate the Special Event Trigger. 2: SEVTCMP<14:0> is compared with PTMR<14:0> to generate the Special Event Trigger.  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 ...

  • Page 184

    ... R/W-0 R/W-0 — PMOD4 PMOD3 R/W-1 R/W-1 R/W-1 (1) (1) (1) PEN1H PEN4L PEN3L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 PMOD2 PMOD1 bit 8 R/W-1 R/W-1 (1) (1) (1) PEN2L PEN1L bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 185

    ... Output overrides via the OVDCON register occur on next T bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled  2009 Microchip Technology Inc. U-0 R/W-0 R/W-0 — ...

  • Page 186

    ... DTA<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit A bits DS70594B-page 186 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 187

    ... Dead time provided from Unit Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit Dead time provided from Unit A  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

  • Page 188

    ... DS70594B-page 188 R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H FAOV2L U-0 R/W-0 R/W-0 — FAEN4 FAEN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 FAOV1H FAOV1L bit 8 R/W-0 R/W-0 FAEN2 FAEN1 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 189

    ... PWM2H/PWM2L pin pair is not controlled by Fault Input B bit 0 FBEN1: Fault Input B Enable bit 1 = PWM1H/PWM1L pin pair is controlled by Fault Input PWM1H/PWM1L pin pair is not controlled by Fault Input B Note 1: Fault A pin has priority over Fault B pin, if enabled.  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 FBOV3L FBOV2H FBOV2L ...

  • Page 190

    ... DS70594B-page 190 R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 191

    ... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC2<15:0>: PWM Duty Cycle #2 Value bits  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

  • Page 192

    ... Bit is cleared R/W-0 R/W-0 R/W-0 PDC4<15:8> R/W-0 R/W-0 R/W-0 PDC4<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 193

    ... Existing Pin Logic 0 UPDNx Up/Down 1  2009 Microchip Technology Inc. This section describes the Quadrature Encoder Inter- face (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. The operational features of the QEI include the following: • ...

  • Page 194

    ... When configured for QEI mode, the control bit is a ‘don’t care’. DS70594B-page 194 R-0 R/W-0 R/W-0 INDEX UPDN R/W-0 R/W-0 R/W-0 TQCKPS<1:0> POSRES U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 QEIM<2:0> bit 8 R/W-0 R/W-0 (1) TQCS UPDN_SRC bit Bit is unknown  2009 Microchip Technology Inc. ...

  • Page 195

    ... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/status bit, UPDN (QEICON<11>), defines Position Counter (POSxCNT) direction Note 1: When configured for QEI mode, the control bit is a ‘don’t care’.  2009 Microchip Technology Inc. ) Preliminary (1) DS70594B-page 195 ...

  • Page 196

    ... Unimplemented: Read as ‘0’ DS70594B-page 196 U-0 U-0 R/W-0 — — IMV<2:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. R/W-0 R/W-0 CEID bit 8 U-0 U-0 — — bit Bit is unknown ...

  • Page 197

    ... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF  2009 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, ADC, etc. The SPI module is ...

  • Page 198

    ... DS70594B-page 198 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...

  • Page 199

    ... The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both the primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1.  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...

  • Page 200

    ... The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both the primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70594B-page 200 (2) (2) Preliminary  2009 Microchip Technology Inc. ...