DSPIC33FJ128MC708A-I/PT Microchip Technology, DSPIC33FJ128MC708A-I/PT Datasheet - Page 260

• Manufacturer Part Number: DSPIC33FJ128MC708A-I/PT
• Description: IC DSPIC MCU/DSP 128K 80-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC708A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 36-chx10-bit|36-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJXXXMCX06A/X08A/X10A
23.2
All of the dsPIC33FJXXXMCX06A/X08A/X10A devices
power their core digital logic at a nominal 2.5V. This
may create an issue for designs that are required to
operate at a higher typical voltage, such as 3.3V. To
simplify
dsPIC33FJXXXMCX06A/X08A/X10A
porate an on-chip regulator that allows the device to
run its core logic from V
The regulator provides power to the core from the other
V
than 5 ohms) capacitor (such as tantalum or ceramic)
be connected to the V
This helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Table 26-13 of Section 26.1 “DC Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 23-1:
DS70594B-page 260
DD
Note 1:
Note:
pins. The regulator requires that a low-ESR (less
2:
On-Chip Voltage Regulator
C
,
system
EFC
STARTUP
it takes approximately 20 s for the on-chip
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
These are typical operating voltages. Refer to
TABLE 26-13: “Internal Voltage Regulator
Specifications” located in Section 26.1 “DC
Characteristics” for the full operating ranges
of V
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
CAP
CAP
3.3V
DD
/V
/V
and V
DDCORE
DDCORE
design,
is applied every time the device
CAP
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
DD
CAP
DD
CAP
SS
/V
dsPIC33F
.
STARTUP
pin.
/V
pin.
/V
DDCORE
DDCORE
DDCORE
all
, code execution is
devices
.
(2)
pin (Figure 23-1).
(1)
family
in
incor-
Preliminary
the
23.3
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the
regulated supply voltage, V
purpose of the BOR module is to generate a device
Reset when a brown-out condition occurs. Brown-out
conditions are generally caused by glitches on the AC
mains (i.e., missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (T
applied before the internal Reset is released. If
T
nominal delay of T
delay in this case is T
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should V
voltage.
PWRT
= 0 and a crystal oscillator is being used, then a
BOR: Brown-out Reset
DD
FSCM
FSCM
fall below the BOR threshold
 2009 Microchip Technology Inc.
= 100 is applied. The total
.
CAP
/V
DDCORE
PWRT
. The main
) will be