ATXMEGA192D3-AU Atmel, ATXMEGA192D3-AU Datasheet - Page 25

MCU AVR 192K FLASH 64TQFP

ATXMEGA192D3-AU

Manufacturer Part Number
ATXMEGA192D3-AU
Description
MCU AVR 192K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA192D3-AU

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
192KB (96K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
ATXMEGA
No. Of I/o's
50
Eeprom Memory Size
2KB
Ram Memory Size
16KB
Cpu Speed
32MHz
Rohs Compliant
Yes
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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14. PMIC - Programmable Multi-level Interrupt Controller
14.1
14.2
14.3
Table 14-1.
8068T–AVR–12/10
Program Address
(Base Address)
Features
Overview
Interrupt vectors
0x00C
0x01C
0x03D
0x03E
0x000
0x002
0x004
0x008
0x014
0x018
0x028
0x030
0x032
Reset and Interrupt Vectors
Source
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
DMA_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
TCC1_INT_base
SPIC_INT_vect
USARTC0_INT_base
USARTC1_INT_base
AES_INT_vect
XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown
in
each peripheral in the XMEGA A manual. For peripherals or modules that have only one inter-
rupt, the interrupt vector is shown in
Separate interrupt vector for each interrupt
Short, predictable interrupt response time
Programmable Multi-level Interrupt Controller
Interrupt vectors can be moved to the start of the Boot Section
Table
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
14-1. Offset addresses for each interrupt available in the peripheral are described for
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
DMA Controller Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
USART 1 on port C Interrupt base
AES Interrupt vector
Table
14-1. The program address is the word address.
XMEGA A3
25

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