ATXMEGA192D3-AU Atmel, ATXMEGA192D3-AU Datasheet - Page 48

MCU AVR 192K FLASH 64TQFP

ATXMEGA192D3-AU

Manufacturer Part Number
ATXMEGA192D3-AU
Description
MCU AVR 192K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA192D3-AU

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
192KB (96K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
ATXMEGA
No. Of I/o's
50
Eeprom Memory Size
2KB
Ram Memory Size
16KB
Cpu Speed
32MHz
Rohs Compliant
Yes
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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29. Program and Debug Interfaces
29.1
29.2
29.3
29.3.1
29.3.2
8068T–AVR–12/10
Features
Overview
IEEE 1149.1 (JTAG) Boundary-scan
Boundary-scan Order
Boundary-scan Description Language Files
The programming and debug facilities are accessed through the JTAG and PDI physical inter-
faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no
general purpose pins are used. JTAG uses four general purpose pins on PORTB.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and
boundary scan.
Table 30-8 on page 53
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,
since these pins constitute the TAP pins when the JTAG is enabled.
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATxmega256/192/128/64A3 devices.
See
PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
JTAG Interface (IEEE std. 1149.1 compliant)
Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)
Access to the OCD system
Programming of Flash, EEPROM, Fuses and Lock Bits
Table 30-8 on page 53
shows the Scan order between TDI and TDO when the Boundary-scan
for ATxmega256/192/128/64A3 Boundary Scan Order.
XMEGA A3
48

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