PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet

MCU PIC 16BIT FLASH 256K 64VQFN

PIC24FJ256DA206-I/MR

Manufacturer Part Number
PIC24FJ256DA206-I/MR
Description
MCU PIC 16BIT FLASH 256K 64VQFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets

Specifications of PIC24FJ256DA206-I/MR

Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
64-VFQFN, Exposed Pad
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
52
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
UART, SPI, USB, I2C, RS-485, RS-232
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
23
Number Of Timers
5
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC24FJ256DA210 Family
Data Sheet
64/100-Pin,
16-Bit Flash Microcontrollers
with Graphics Controller and
USB On-The-Go (OTG)
 2010 Microchip Technology Inc.
DS39969B

Related parts for PIC24FJ256DA206-I/MR

PIC24FJ256DA206-I/MR Summary of contents

Page 1

... PIC24FJ256DA210 Family  2010 Microchip Technology Inc. Data Sheet 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG) 64/100-Pin, DS39969B ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... PIC24FJ256DA106 64 256K PIC24FJ128DA110 100/121 128K PIC24FJ256DA110 100/121 256K PIC24FJ128DA206 64 128K PIC24FJ256DA206 64 256K PIC24FJ128DA210 100/121 128K PIC24FJ256DA210 100/121 256K  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Peripheral Features: • Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP), 100-pin devices only: - Direct access from CPU with an Extended Data ...

Page 4

... In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words  2010 Microchip Technology Inc. ...

Page 5

... AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 PGEC1/AN1/V -/RP1/CN3/RB1 REF PGED1/AN0/V +/RP0/CN2/RB0 REF Note 1: The back pad on QFN devices should be connected to V Legend: RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant +5.5V.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY PIC24FJXXXDAX06 ...

Page 6

... SS 42 RTCC/DMLN/RP2/CN53/RD8 43 DPLN/SDA1/RP4/GD8/CN54/RD9 44 SCL1/RP3/GD6/CN55/RD10 45 RP12/GD7/CN56/RD11 46 DMH/RP11/INT0/CN49/RD0 47 SOSCI/C3IND/CN1/RC13 48 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 49 V /RP24/GD9/V /CN50/RD1 CPCON BUSCHG 50 DPH/RP23/CN51/RD2 51 RP22/GEN/CN52/RD3 52 RP25/GCLK/CN13/RD4 53 RP20/GPWR/CN14/RD5 54 C3INB/CN15/RD6 55 C3INA/SESSEND/CN16/RD7 56 V CAP 57 ENVREG 58 GD10/V /V 1/V /CN68/RF0 BUSST CMPST BUSVLD 59 GD11/V 2/SESSVLD/CN69/RF1 CMPST 60 GD0/CN58/RE0 61 GD1/CN59/RE1 62 GD2/CN60/RE2 63 GD3/CN61/RE3 64 HSYNC/CN62/RE4  2010 Microchip Technology Inc. ...

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... PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 21 AN3/C2INA/GD5/VPIO/CN5/RB3 22 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 23 PGEC1/AN1/V -/RP1/CN3/RB1 REF 24 PGED1/AN0/V +/RP0/CN2/RB0 REF 25 Legend: RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant +5.5V.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY PIC24FJXXXDAX10 SOSCO/SCLKI/TICK/C3INC/ 74 RPI37/CN0/RC14 73 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 72 RP12/PMA14/PMCS1/CN56/RD11 71 RP3/PMA15/PMCS2/CN55/ 70 RD10 DPLN/RP4/GD10/PMACK2/CN54/ ...

Page 8

... TDI/PMA21/PMA3 61 TDO/CN38/RA5 OSCI/CLKI/CN23/RC12 63 64 OSCO/CLKO/CN22/RC15 SCL1/RPI36/PMA22/PMCS2 67 SDA1/RPI35/PMBE1/CN44/RA15 68 DMLN/RTCC/RP2/CN53/RD8 69 DPLN/RP4/GD10/PMACK2/CN54/RD9 70 RP3/PMA15/PMCS2 71 RP12/PMA14/PMCS1 72 DMH/RP11/INT0/CN49/RD0 73 SOSCI/C3IND/CN1/RC13 74 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 /RP24/GD7/V CPCON 77 DPH/RP23/GD11/PMACK1/CN51/RD2 78 RP22/PMBE0/CN52/RD3 79 RPI42/PMD12/CN57/RD12 80 PMD13/CN19/RD13 + and V - when the ALTVREF Configuration bit is programmed. REF Function (2) /CN36/RA3 (2) /CN37/RA4 (2) /CN43/RA14 (3) /CN55/RD10 (3) /CN56/RD11 /CN50/RD1 BUSCHG  2010 Microchip Technology Inc. ...

Page 9

... RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for V REF 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Pin 91 AN23/GEN/CN39/RA6 92 AN22/PMA17/CN40/RA7 93 PMD0/CN58/RE0 ...

Page 10

... SS V RC13 RD11 DD RD0 n/c RD10 RD8 GD10/ RA14 RD9 OSCI/ V OSCO RC12 RC15 N/C RA5 RA4 RA3 V / D+/RG2 RA2 USB N/C N/C GD9/RF8 D-/RG3 GD15/ USBID/ GD3/ DD RD15 RF3 RF2 GD14/ RF4 RF5 RD14  2010 Microchip Technology Inc. ...

Page 11

... RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Note 1: Alternate pin assignments for V REF 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Pin PMD9/CN78/RG1 E7 ...

Page 12

... Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’. DS39969B-page 12 Pin L1 PGEC2/AN6/RP6/CN24/RB6 ( /PMA7/CN41/RA9 REF L3 AVSS L4 AN9/RP9/GD13/CN27/RB9 L5 AN10/CV REF L6 RP31/GD2/CN76/RF13 L7 AN13/PMA10/CTEDG1/CN31/RB13 L8 AN15/REFO/RP29/PMA0/CN12/RB15 L9 RPI43/GD14/CN20/RD14 L10 RP10/PMA9/CN17/RF4 L11 RP17/GD5/PMA8/SCL2/CN18/RF5 — — — + and V - when the ALTVREF Configuration bit is programmed. REF Function /PMA13/CN28/RB10 — — —  2010 Microchip Technology Inc. ...

Page 13

... Electrical Characteristics .......................................................................................................................................................... 371 31.0 Packaging Information.............................................................................................................................................................. 387 Appendix A: Revision History............................................................................................................................................................. 397 Index ................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 405 Customer Change Notification Service .............................................................................................................................................. 405 Customer Support .............................................................................................................................................................................. 405 Reader Response .............................................................................................................................................................................. 406 Product Identification System ............................................................................................................................................................ 407  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY DS39969B-page 13 ...

Page 14

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39969B-page 14  2010 Microchip Technology Inc. ...

Page 15

... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ128DA106 • PIC24FJ128DA206 • PIC24FJ256DA106 • PIC24FJ256DA206 • PIC24FJ128DA110 • PIC24FJ128DA210 • PIC24FJ256DA110 • PIC24FJ256DA210 The PIC24FJ256DA210 family enhances on the exist- ing line of Microchip‘s 16-bit microcontrollers, adding a ...

Page 16

... Master modes. • Real-Time Clock and Calendar: (RTCC) This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 2 C™  2010 Microchip Technology Inc. ...

Page 17

... Available I/O pins and ports (52 pins on 6 ports for PIC24FJXXXDAX06 devices and 84 pins on 7 ports for PIC24FJXXXDAX10 devices). 4. Available Interrupt-on-Change Notification (ICN) inputs (52 on PIC24FJXXXDAx06 devices and 84 on PIC24FJXXXDAX10 devices).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 5. Available remappable PIC24FJXXXDAX06 devices and 44 pins on PIC24FJXXXDAX10 devices). ...

Page 18

... Yes Yes Yes Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP and QFN PIC24FJ128DA206 PIC24FJ256DA206 128K 256K 44,032 87,552 96K 52 (1) 2 (1) ...

Page 19

... Module (input channels) Analog Comparators CTMU Interface USB OTG Graphics Controller Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA210 PIC24FJ256DA210 DC – 32 MHz 128K 256K 44,032 87,552 24K 66 (62/4) ...

Page 20

... RTCC Comparators ADC SPI 2 UART I C ™ (2) 1/2/3 (2) 1/2/3 1/2/3/4 (1) PORTA 16 (12 I/O) PORTB (16 I/ (1) PORTC (8 I/ (1) PORTD (16 I/O) (1) PORTE (10 I/O) (1) PORTF 16-Bit ALU (10 I/O) 16 (1) PORTG (12 I/O) USB OTG (3) EPMP/PSP Graphics (2) CTMU Controller  2010 Microchip Technology Inc. ...

Page 21

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 22

... ALTVREF (CW1<5>) bit is programmed to ‘0’. REF DS39969B-page 22 Input I/O 121-Pin Buffer BGA B11 I ST C10 L10 I ST L11 Interrupt-on-Change Inputs F11 H11 I ST G10 I ST G11 Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 23

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 24

... Graphics Display Horizontal Sync Pulse External Interrupt Input Master Clear (device Reset) Input. This line is brought low to cause a Reset ANA Main Oscillator Input Connection. F11 O ANA Main Oscillator Output Connection Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 25

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 26

... ST/TTL Parallel Master Port Read Strobe. C8 I/O ST/TTL Parallel Master Port Write Strobe I/O ST H11 I/O ST G10 I/O ST G11 I I/O ST PORTA Digital I/ I/O ST E11 I I Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 27

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 28

... ST A1 I/O ST PORTE Digital I/ — Reference Clock Output I/O ST K11 I/O ST K10 I/O ST L10 I/O ST PORTF Digital I/O. L11 I I/O ST J10 Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 29

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 30

... Boost Generator, Comparator Input 3. BUS USB V Boost Generator, Comparator Input 2. BUS C10 I ANA Secondary Oscillator/Timer1 Clock Input. B11 O ANA Secondary Oscillator/Timer1 Clock Output. B11 I ST Timer1 Clock Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 31

... The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate V pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. REF  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Input I/O 121-Pin Buffer BGA ...

Page 32

... PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 32  2010 Microchip Technology Inc. ...

Page 33

... REF REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 2- MCLR (2) C6 ...

Page 34

... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL  2010 Microchip Technology Inc. ...

Page 35

... When the regulator is disabled, the V CAP must be tied to a voltage supply at the V Refer to Section 30.0 “Electrical Characteristics” for information on V and DDCORE  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 2- 0.1 0.01 0.001 0.01 Note: Data for Murata GRM21BF50J106ZE01 shown. ...

Page 36

... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSCI ` OSCO GND ` SOSCO SOSC I ` Sec Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1  2010 Microchip Technology Inc. ...

Page 37

... Microchip Technology Inc. PIC24FJ256DA210 FAMILY If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: • ...

Page 38

... PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 38  2010 Microchip Technology Inc. ...

Page 39

... All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY The core supports Inherent (no operand), Relative, Literal, Memory Direct Addressing modes along with three groups of addressing modes ...

Page 40

... ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Repeat Loop Counter Register CPU Control Register Disable Interrupt Count Register Data Space Read Page Register Data Space Write Page Register Peripheral Modules  2010 Microchip Technology Inc. ...

Page 41

... FIGURE 3-2: PROGRAMMER’S MODEL W0 (WREG) Divider Working Registers Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Frame Pointer Stack Pointer SPLIM TBLPAG 9 DSRPAG 8 DSWPAG ...

Page 42

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th low-order bit (for byte-sized data low-order bit of the result has occurred (1,2) U-0 U-0 R/W-0, HSC — — DC bit bit Bit is unknown th low-order bit (for word-sized data)  2010 Microchip Technology Inc. ...

Page 43

... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — ...

Page 44

... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided in Table 3-2. Description  2010 Microchip Technology Inc. ...

Page 45

... FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES Note: Memory areas are not shown to scale.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces” ...

Page 46

... Device PIC24FJ128DAXXX PIC24FJ256DAXXX least significant word Instruction Width Word for devices in the FLASH CONFIGURATION WORDS FOR PIC24FJ256DA210 FAMILY DEVICES Program Configuration Memory Word Addresses (Words) 0x0157F8:0x0157FE 44,032 87,552 0x02ABF8:0x02ABFE PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006  2010 Microchip Technology Inc. ...

Page 47

... PIC24FJXXXDA106 24 Kbytes Note 1: The internal RAM above 30 Kbytes can be accessed through EDS window.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY The EDS includes any additional internal data memory not accessible by the lower 32-Kbyte data address space and any external memory through EPMP. For more details on accessing internal extended data memory, refer to the “ ...

Page 48

... EDS Page 0x300 FFFEh EDS Page 0x3FF (4) Near Data Space Internal Extended (2) Data RAM(66 Kbytes) (3) EPMP Memory Space Program Space Visibility Area to Access Lower Word of Program Memory Program Space Visibility Area to Access Upper Word of Program Memory  2010 Microchip Technology Inc. ...

Page 49

... EPMP RTC/Comp 700h GFX Controller Legend: — implemented SFRs in this block  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. ® MCUs and Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words ...

Page 50

TABLE 4-4: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...

Page 51

TABLE 4-5: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE (1) (1) (1) (1) CNPD3 005A CN47PDE CN46PDE CN45PDE CN44PDE CN43PDE CNPD4 ...

Page 52

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...

Page 53

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 IPC18 00C8 — — — — IPC19 00CA — — — — IPC20 00CC — U3TXIP2 ...

Page 54

TABLE 4-8: INPUT CAPTURE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IC1CON1 0140 — — ICSIDL ICTSEL2 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ICTSEL2 IC2CON2 ...

Page 55

TABLE 4-9: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A — — OCSIDL ...

Page 56

TABLE 4-9: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC8CON1 01D6 — — OCSIDL OCTSEL2 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 — — ...

Page 57

TABLE 4-11: UART REGISTER MAPS File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...

Page 58

TABLE 4-12: SPI REGISTER MAPS File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — SPI1BUF 0248 SPI2STAT 0260 SPIEN — ...

Page 59

TABLE 4-15: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02D0 TRISC15 TRISC14 TRISC13 TRISC12 (2,3) (2) PORTC 02D2 RC15 RC14 RC13 RC12 LATC 02D4 LATC15 LATC14 LATC13 LATC12 ODCC 02D6 ODC15 ODC14 ...

Page 60

TABLE 4-18: PORTF REGISTER MAP File (1) (1) Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISF 02E8 — — TRISF13 TRISF12 PORTF 02EA — — RF13 RF12 LATF 02EC — — LATF13 LATF12 ODCF 02EE — — ...

Page 61

TABLE 4-21: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...

Page 62

TABLE 4-21: ADC REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name AD1CON1 0320 ADON — ADSIDL — AD1CON2 0322 VCFG2 VCFG1 VCFG0 r AD1CON3 0324 ADRC r r SAMC4 AD1CHS 0328 CH0NB — — ...

Page 63

TABLE 4-23: USB OTG REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (2) U1OTGIR 0480 — — — — (2) U1OTGIE 0482 — — — — 2) U1OTGSTAT 0484 — — — — (2) U1OTGCON ...

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TABLE 4-23: USB OTG REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1EP10 04BE — — — — U1EP11 04C0 — — — — U1EP12 04C2 — — — — U1EP13 04C4 — — ...

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TABLE 4-26: ENHANCED PARALLEL MASTER/SLAVE PORT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name PMCON1 0600 PMPEN — PSIDL ADRMUX1 PMCON2 0602 BUSY — ERROR TIMEOUT PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN PMCON4 0606 PTEN15 ...

Page 66

TABLE 4-28: COMPARATORS REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CMSTAT 0630 CMIDL — — — CVRCON 0632 — — — — CM1CON 0634 CON COE CPOL — CM2CON 0636 CON COE CPOL — ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — INT1R5 INT1R4 RPINR1 0682 — — INT3R5 INT3R4 RPINR2 0684 — — — — RPINR3 0686 — — ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — RP1R5 RP1R4 RPOR1 06C2 — — RP3R5 RP3R4 (1) (1) RPOR2 06C4 — — RP5R5 RP5R4 RPOR3 ...

Page 69

TABLE 4-31: GRAPHICS REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 G1CMDL 0700 G1CMDH 0702 G1CON1 0704 G1EN — G1SIDL GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0 G1STAT 0706 PUBUSY — — — G1IE 0708 PUIE — ...

Page 70

TABLE 4-32: SYSTEM REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 CLKDIV2 0746 GCLKDIV6 GCLKDIV5 GCLKDIV4 GCLKDIV3 ...

Page 71

... Available only in PIC24FJXXXDA2XX devices. In the PIC24FJXXXDA110 devices, this space can be used to access external memory using EPMP. 2: Available only in PIC24FJXXXDAX10 devices (100-pin).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY pages, each having 32 Kbytes of data. Mapping of the EDS page into the EDS window is done using the Data ...

Page 72

... Therefore, a minimum of two instruction cycles is required to complete an EDS read. EDS reads under the REPEAT instruction; the first two accesses take three accesses take one cycle. Wn<0> is Byte Select cycles and the subsequent  2010 Microchip Technology Inc. ...

Page 73

... EDS writes  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY EDS window is enabled by setting bit 15 of the working register, assigned with the offset address, and the accessed location can be written. Figure 4-2 illustrates how the EDS space address is generated for write operations ...

Page 74

... Near data (2) 0x001FFF space 0x002000 to 0x007FFF 0x008000 to 0x00FFFE 32 Kbytes on 0x010000 to each page 0x017FFE 0x018000 to Only 2 Kbytes 0x0187FE of extended SRAM on this page 0x018800 to 0x027FFE • EPMP • memory • (4) space 0xFF8000 to 0xFFFFFE Invalid Address Address error (3) trap  2010 Microchip Technology Inc. ...

Page 75

... Free Word W15 ( POP : [--W15] PUSH : [W15++]  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...

Page 76

... Bits 24 Bits Select 1 DSRPAG<7:0> Bits 23 Bits <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (2) (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits EA 1/0 15 Bits Byte Select  2010 Microchip Technology Inc. ...

Page 77

... FIGURE 4-9: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...

Page 78

... Mbytes) for read • operations only. 0x7F8000 to 0x7FFFFE 0x000001 to 0x007FFF Upper words of 4M program instructions • (4 Mbytes remaining, • 4 Mbytes are phantom • bytes) for read 0x7F8001 to 0x7FFFFF operations only. Invalid Address Address error trap  2010 Microchip Technology Inc. Comment (1) ...

Page 79

... When DSRPAG<9:8> = and EA<15> Program Space DSRPAG 23 15 302h The data in the page designated by DSRPAG is mapped into the upper half of the data memory space....  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 1 Data Space 0 000000h 010000h 017FFEh EDS Window 7FFFFEh 1 Data Space 0 ...

Page 80

... DS39969B-page 80 ;page 0x202, consisting lower words, is selected for read ;select the location (0x0A read ;set the MSB of the base address, enable EDS mode ;read Low byte ;read High byte ; ;two word read, stored in w2 and w3  2010 Microchip Technology Inc. ...

Page 81

... Counter Using Table Instruction User/Configuration Space Select  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- Manual” ...

Page 82

... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the opera- tion and the WR bit is automatically cleared when the operation is finished.  2010 Microchip Technology Inc. ...

Page 83

... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only; refer to the device programming specification.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY (1) U-0 U-0 — — ...

Page 84

... Initialize in-page EA<15:0> pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted  2010 Microchip Technology Inc. ...

Page 85

... BSET NVMCON, #WR NOP NOP BTSC NVMCON, #15 BRA $-2  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...

Page 86

... Data to program upper byte // Initialize NVMCON // Initialize PM Page Boundary SFR // Initialize lower word of address // Write to address low word // Write to upper byte // Block interrupts with priority <7 // for next 5 instructions // C30 function to perform unlock // sequence and set WR  2010 Microchip Technology Inc. ...

Page 87

... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...

Page 88

... R/W-0, HS R/W-0, HS R/W-0, HS (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (2) U-0 R/W-0, HS R/W-0 (3) — CM VREGS bit 8 R/W-1, HS R/W-1, HS BOR POR bit Bit is unknown , when waking up from VREG  2010 Microchip Technology Inc. ...

Page 89

... PWRSAV #0 Instruction IDLE (RCON<2>) PWRSAV #1 Instruction BOR (RCON<1>) POR, BOR POR (RCON<0>) POR Note: All Reset flag bits may be set or cleared by the user software.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY (1) (CONTINUED) VREG Setting Event , when waking up from Clearing Event POR ...

Page 90

... Manual”, Section 8.0 “Oscillator Configuration” for further details. TABLE 6-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Reset Type Clock Source Determinant POR FNOSC Configuration bits (CW2<10:8>) BOR MCLR COSC Control bits WDTO (OSCCON<14:12>) SWR  2010 Microchip Technology Inc. ...

Page 91

... The device will not begin to execute code until a valid clock source has been released to the system. There- fore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY System Clock SYSRST Delay ...

Page 92

... PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 92  2010 Microchip Technology Inc. ...

Page 93

... PIC24FJ256DA210 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. The ALTIVT (INTCON2< ...

Page 94

... Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 000112h Reserved (1) (1) Trap Source  2010 Microchip Technology Inc. ...

Page 95

... Enhanced Parallel Master Port (EPMP) Real-Time Clock and Calendar (RTCC) SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Vector IVT AIVT Number Address Address 13 00002Eh 00012Eh IFS0< ...

Page 96

... IEC0<3> IPC0<14:12> IEC0<7> IPC1<14:12> IEC0<8> IPC2<2:0> IEC1<11> IPC6<14:12> IEC1<12> IPC7<2:0> IEC4<1> IPC16<6:4> IEC0<11> IPC2<14:12> IEC0<12> IPC3<2:0> IEC4<2> IPC16<10:8> IEC1<14> IPC7<10:8> IEC1<15> IPC7<14:12> IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> IEC5<7> IPC21<14:12> IEC5<8> IPC22<2:0> IEC5<9> IPC22<6:4> IEC5<6> IPC21<10:8>  2010 Microchip Technology Inc. ...

Page 97

... The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY a generic ISR is used for multiple vectors (such as when ISR remapping is used in bootloader applica- tions check if another interrupt is pending while in an ISR ...

Page 98

... U-0 R/C-0, HSC r-1 (1) — IPL3 Clearable bit HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown (1) U-0 U-0 — — bit 8 U-0 U-0 — — bit 0  2010 Microchip Technology Inc. ...

Page 99

... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — — ...

Page 100

... Interrupt on positive edge DS39969B-page 100 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT4EP INT3EP INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 101

... T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF ...

Page 102

... Interrupt request has not occurred DS39969B-page 102 R/W-0, HS R/W-0, HS R/W-0, HS T5IF T4IF OC4IF R/W-0, HS R/W-0, HS R/W-0, HS INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0, HS U-0 OC3IF — bit 8 R/W-0, HS R/W-0, HS MI2C1IF SI2C1IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 103

... Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Not available in PIC24FJXXXDAX06 devices.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS (1) OC8IF OC7IF ...

Page 104

... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Not available in PIC24FJXXXDAX06 devices. DS39969B-page 104  2010 Microchip Technology Inc. ...

Page 105

... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — — — ...

Page 106

... Unimplemented: Read as ‘0’ DS39969B-page 106 U-0 U-0 U-0 — — — U-0 R/W-0, HS R/W-0, HS — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 R/W-0, HS — LVDIF bit 8 R/W-0, HS U-0 U1ERIF — bit Bit is unknown ...

Page 107

... U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS OC9IF SPI3IF ...

Page 108

... Unimplemented: Read as ‘0’ DS39969B-page 108 U-0 U-0 U-0 — — — R/W-0, HS U-0 U-0 GFX1IF — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 109

... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...

Page 110

... See Section 10.4 “Peripheral Pin Select (PPS)” for more information. DS39969B-page 110 R/W-0 R/W-0 (1) T5IE T4IE R/W-0 R/W-0 (1) INT1IE CNIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 U-0 OC4IE OC3IE — bit 8 R/W-0 R/W-0 R/W-0 CMIE MI2C1IE SI2C1IE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 111

... Interrupt request is enabled 0 = Interrupt request is not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY (1) DS39969B-page 111 ...

Page 112

... Not available in 64-pin devices (PIC24FJXXXDAX06). DS39969B-page 112 R/W-0 R/W-0 (1) OC8IE OC7IE U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 R/W-0 OC6IE OC5IE IC6IE bit 8 U-0 R/W-0 R/W-0 — SPI2IE SPF2IE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 113

... Unimplemented: Read as ‘0’ Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 — ...

Page 114

... Unimplemented: Read as ‘0’ DS39969B-page 114 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIE U2ERIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 R/W-0 — LVDIE bit 8 R/W-0 U-0 U1ERIE — bit Bit is unknown ...

Page 115

... U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 OC9IE SPI3IE SPF3IE ...

Page 116

... Unimplemented: Read as ‘0’ DS39969B-page 116 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 GFX1IE — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 117

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...

Page 118

... Unimplemented: Read as ‘0’ DS39969B-page 118 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 119

... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...

Page 120

... Interrupt source is disabled DS39969B-page 120 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 121

... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...

Page 122

... Interrupt source is disabled DS39969B-page 122 R/W-0 U-0 R/W-1 IC8IP0 — IC7IP2 U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP1 IC7IP0 bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 123

... OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 ...

Page 124

... Interrupt source is disabled DS39969B-page 124 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 125

... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 ...

Page 126

... Unimplemented: Read as ‘0’ DS39969B-page 126 R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC4IP1 IC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 127

... Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 ...

Page 128

... DS39969B-page 128 U-0 U-0 — — R/W-0 U-0 R/W-1 (1) (1) PMPIP0 — OC8IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 OC8IP1 OC8IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 129

... SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 ...

Page 130

... Unimplemented: Read as ‘0’ DS39969B-page 130 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 INT4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 131

... RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...

Page 132

... Unimplemented: Read as ‘0’ DS39969B-page 132 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 133

... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — — — U-0 ...

Page 134

... Unimplemented: Read as ‘0’ DS39969B-page 134 R/W-0 U-0 R/W-1 U3TXIP0 — U3RXIP2 R/W-0 U-0 U-0 U3ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U3RXIP1 U3RXIP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 135

... Unimplemented: Read as ‘0’ bit 2-0 SI2C3IP<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 — USB1IP2 R/W-0 ...

Page 136

... Interrupt source is disabled DS39969B-page 136 R/W-0 U-0 R/W-1 SPI3IP0 — SPF3IP2 R/W-0 U-0 R/W-1 U4TXIP0 — U4RXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF3IP1 SPF3IP0 bit 8 R/W-0 R/W-0 U4RXIP1 U4RXIP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 137

... Unimplemented: Read as ‘0’ bit 2-0 OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — — — R/W-0 ...

Page 138

... Interrupt source is disabled DS39969B-page 138 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — GFX1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 GFX1IP1 GFX1IP0 bit Bit is unknown ...

Page 139

... VHOLD = 1: The VECNUM bits indicate the vector number (from 0 to 118) of the last interrupt to occur VHOLD = 0: The VECNUM bits indicate the vector number (from 0 to 118) of the interrupt request currently being handled  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 R-0, HSC R-0, HSC — ...

Page 140

... Note that only user interrupts with a priority level less can be disabled. Trap sources (Level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels, 1-6, for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction.  2010 Microchip Technology Inc. ...

Page 141

... Enable SOSCI Oscillator Note 1: Refer to Figure 8-2 for more information on the 96 MHz PLL block.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY • An on-chip PLL block to boost internal operating frequency on select internal and external oscillator sources, and to provide a precise clock source for peripherals, such as USB and graphics • ...

Page 142

... Oscillator Source POSCMD<1:0> Internal 11 Internal 11 Internal 11 Secondary 11 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 bits, FNOSC<2:0> (Configuration Configuration bits (Configuration FNOSC<2:0> Notes 1, 2 111 1 110 1 101 1 100 — 011 1 011 — 010 — 010 1 010 1 001 1 000  2010 Microchip Technology Inc. ...

Page 143

... IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY The OSCCON register (Register 8-1) is the main con- trol register for the oscillator ...

Page 144

... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected. DS39969B-page 144 (1) (2) (3)  2010 Microchip Technology Inc. ...

Page 145

... MHz (divide MHz (divide MHz (divide by 1) Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN ...

Page 146

... DS39969B-page 146 U-0 U-0 — — R/W-0 R/W-0 (1) (1) (1) TUN4 TUN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 147

... MHz (divide by 1.25); from here, increment the divisor by 0.25 0000000 = (0) 96.00 MHz (divide by 1) bit 8-0 Unimplemented: Read as ‘0’ Note 1: These bits take effect only when the 96 MHz PLL is enabled.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 (1) ...

Page 148

... Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL modes are not permitted. This applies to clock switches in either direc- tion. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2010 Microchip Technology Inc. ...

Page 149

... MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 8.5 96 MHz PLL Block The 96 MHz PLL block is implemented to generate the stable 48 MHz clock required for full-speed USB operation, a programmable clock output for the graphics controller module and the system clock from the same oscillator source ...

Page 150

... Graphics Clock Option 2 ÷ 64 127 Clock Output for ÷ 63 126 Display Interface ... ... (DISPCLK) ÷ 17.50 65 ÷ 17.00 64 ... ... ÷ 1.25 1 ÷ Clock Output . for Graphics . GCLKDIV<6:0> Controller Module (G1CLK) 32 MHz (16) 16 MHz (8) (1) 8 MHz (4) (1) 4 MHz (2)  2010 Microchip Technology Inc. ...

Page 151

... USB module is not needed (e.g., the application is sleeping and waiting for a bus attachment).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY clock signal from 96 MHz PLL. Due to the requirement that a 4 MHz input must be provided to generate the 96 MHz signal, the oscillator operation is limited to a range of possible values ...

Page 152

... MHz (2.82 MHz) 5.49 MHz (2.74 MHz) 5.33 MHz (2.66 MHz) … 2.95 MHz (1.47 MHz) 2.91 MHz (1.45 MHz) 2.82 MHz (1.41 MHz) 2.74 MHz (1.37 MHz) … 1.52 MHz (762 kHz) 1.50 MHz (750 kHz)  2010 Microchip Technology Inc. ...

Page 153

... Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ Note 1: Note that the crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 (1) ROSEL ...

Page 154

... PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 154  2010 Microchip Technology Inc. ...

Page 155

... PWRSAV instruction is shown in Example 9-1. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “wake-up”.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 9.2.1 SLEEP MODE Sleep mode has these features: • ...

Page 156

... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows possible further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.  2010 Microchip Technology Inc. ...

Page 157

... CK WR PORT Data Latch Read LAT Read PORT  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...

Page 158

... Make sure to disable the analog output function on 0 the pin if any is present. Tolerated Input V Only Tolerates input levels above V 5.5V for most standard logic. . Voltage excursions DD Comments Description input levels are tolerated. , useful DD  2010 Microchip Technology Inc. ...

Page 159

... Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ Note 1: This register is not available on 64-pin devices (PIC24FJXXXDAX06).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 R/W-1 — ...

Page 160

... ANSC4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 ANSB9 ANSB8 bit 8 R/W-1 R/W-1 ANSB1 ANSB0 bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 161

... Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 8-0 Unimplemented: Read as ‘0’ Note 1: This register is not available in 64-pin devices (PIC24FJXXXDAX06).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — ...

Page 162

... U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 R/W-1 — ANSF0 bit Bit is unknown R/W-1 R/W-1 ANSG9 ...

Page 163

... EXAMPLE 10-2: PORT WRITE/READ IN ‘C’ TRISB = 0xFF00; Nop(); If (PORTBbits.RB13){ };  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the CNPU1 through CNPU6 registers (for pull-ups), and the CNPD1 through CNPD6 registers (for pull-downs) ...

Page 164

... RPn/RPIn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the max- imum number of Peripheral Pin Selections supported by the device.  2010 Microchip Technology Inc ...

Page 165

... UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Function Name Register INT1 RPINR0 INT2 RPINR1 ...

Page 166

... Output Compare 8 U3TX UART3 Transmit (3) U3RTS UART3 Request To Send U4TX UART4 Transmit (3) U4RTS UART4 Request To Send SDO3 SPI3 Data Output SCK3OUT SPI3 Clock Output SS3OUT SPI3 Slave Select Output OC9 Output Compare 9 C3OUT Comparator 3 Output (unused)  2010 Microchip Technology Inc. Null NC ...

Page 167

... Total 64-Pin 28 (PIC24FJXXXDAX06) 100/121-Pin 32 (PIC24FJXXXDAX10)  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 10.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these reg- isters, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON< ...

Page 168

... OSCCON,#6"); ("MOV #OSCCON, w1 \n" "MOV #0x46, w2 \n" "MOV #0x57, w3 \n" "MOV.b w2, [w1]\ n" "MOV.b w3, [w1] \n" "BSET OSCCON, #6") ;  2010 Microchip Technology Inc. ...

Page 169

... INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Note: Input and output register values can only be changed if IOLOCK (OSCCON<6> ...

Page 170

... T2CKR4 T2CKR3 T2CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-1 R/W-1 INT4R1 INT4R0 bit Bit is unknown R/W-1 R/W-1 T3CKR1 T3CKR0 bit 8 R/W-1 R/W-1 T2CKR1 T2CKR0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 171

... IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-1 R/W-1 R/W-1 T5CKR4 ...

Page 172

... IC5R4 IC5R3 IC5R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC4R1 IC4R0 bit 8 R/W-1 R/W-1 IC3R1 IC3R0 bit Bit is unknown R/W-1 R/W-1 IC6R1 IC6R0 bit 8 R/W-1 R/W-1 IC5R1 IC5R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 173

... OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-1 R/W-1 R/W-1 IC8R4 ...

Page 174

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC9R1 IC9R0 bit 8 U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 U3RXR1 U3RXR0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 175

... U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 ...

Page 176

... SS1R4 SS1R3 SS1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 SCK1R1 SCK1R0 bit 8 R/W-1 R/W-1 SDI1R1 SDI1R0 bit Bit is unknown R/W-1 R/W-1 U3CTSR1 U3CTSR0 bit 8 R/W-1 R/W-1 SS1R1 SS1R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 177

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 ...

Page 178

... SDI3R4 SDI3R3 SDI3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 U4CTSR1 U4CTSR0 bit 8 R/W-1 R/W-1 U4RXR1 U4RXR0 bit Bit is unknown R/W-1 R/W-1 SCK3R1 SCK3R0 bit 8 R/W-1 R/W-1 SDI3R1 SDI3R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 179

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 U-0 — — — ...

Page 180

... RP2R4 RP2R3 RP2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP1R1 RP1R0 bit 8 R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP3R1 RP3R0 bit 8 R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 181

... Peripheral output number n is assigned to pin, RP7 (see Table 10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see Table 10-4 for peripheral function numbers).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 (1) (1) ...

Page 182

... RP10R4 RP10R3 RP10R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP9R1 RP9R0 bit 8 R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown R/W-0 R/W-0 RP11R1 RP11R0 bit 8 R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 183

... Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Table 10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 ...

Page 184

... RP18R4 RP18R3 RP18R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP17R1 RP17R0 bit 8 R/W-0 R/W-0 RP16R1 RP16R0 bit Bit is unknown R/W-0 R/W-0 RP19R1 RP19R0 bit 8 R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 185

... Peripheral output number n is assigned to pin, RP23 (see Table 10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see Table 10-4 for peripheral function numbers).  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 ...

Page 186

... RP26R4 RP26R3 RP26R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP25R1 RP25R0 bit 8 R/W-0 R/W-0 RP24R1 RP24R0 bit Bit is unknown R/W-0 R/W-0 RP27R1 RP27R0 bit 8 R/W-0 R/W-0 RP26R1 RP26R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 187

... Unimplemented: Read as ‘0’ bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Table 10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 R/W-0 RP29R4 ...

Page 188

... PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 188  2010 Microchip Technology Inc. ...

Page 189

... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...

Page 190

... DS39969B-page 190 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 191

... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...

Page 192

... The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39969B-page 192 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR5) (TMR4 TMR3HLD (TMR5HLD) TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync  2010 Microchip Technology Inc. ...

Page 193

... Equal Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 2: The ADC event trigger is available only on Timer3.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 1x Gate Sync 01 ...

Page 194

... DS39969B-page 194 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 195

... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY U-0 U-0 (1) — ...

Page 196

... PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 196  2010 Microchip Technology Inc. ...

Page 197

... Trigger Trigger Sources Logic Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 13.1 General Operating Modes 13.1.1 SYNCHRONOUS AND TRIGGER ...

Page 198

... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (performed automatically by hardware).  2010 Microchip Technology Inc. for both modules configure ...

Page 199

... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY R/W-0 R/W-0 ICTSEL2 ...

Page 200

... R/W-0 R/W-1 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (1) (1) (1) (2) (2) (2) (2) (2) (2) (2) U-0 U-0 R/W-0 — — IC32 bit 8 R/W-1 R/W-0 R/W-1 SYNCSEL1 SYNCSEL0 bit Bit is unknown  2010 Microchip Technology Inc. ...

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