ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet

MCU 8BIT 128K ISP FLASH 64-QFN

ATMEGA128A-MU

Manufacturer Part Number
ATMEGA128A-MU
Description
MCU 8BIT 128K ISP FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4KB
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16MHz Throughput at 16MIPS
– On-chip 2-cycle Multiplier
– 128Kbytes of In-System Self-programmable Flash program memory
– 4Kbytes EEPROM
– 4Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64 Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7V - 5.5V
– 0 - 16MHz
Capture Mode
and Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128KBytes
In-System
Programmable
Flash
ATmega128A
Rev. 8151H–AVR–02/11

Related parts for ATMEGA128A-MU

ATMEGA128A-MU Summary of contents

Page 1

... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V • Speed Grades – 16MHz ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 128KBytes In-System Programmable Flash ATmega128A Rev. 8151H–AVR–02/11 ...

Page 2

... The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF package should be soldered to ground. ® ® AVR ATmega128A is a low-power CMOS 8-bit microcontroller based on the AVR ATmega128A 48 PA3 (AD3) 47 PA4 (AD4) 46 PA5 (AD5) 45 PA6 (AD6) 44 PA7 (AD7) ...

Page 3

... PURPOSE REGISTERS ALU STATUS REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTB REG. PORTB PORTB DRIVERS PB0 - PB7 ATmega128A PC0 - PC7 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER OSCILLATOR ...

Page 4

... Atmel ATmega128A is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... The Atmel ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A” describes what the user should be aware of replacing the ATmega103 by an ATmega128A. 2.2.1 ATmega103 Compatibility Mode By programming the M103C fuse, the ATmega128A will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new fea- ...

Page 6

... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128A as listed on page 81. ...

Page 7

... PEN has no function during normal operation. 8151H–AVR–02/11 ® ® AVR ATmega103 compatibility mode, these pins only serves as strobes signals to the 324. Shorter pulses are not guaranteed to generate a reset. , even if the ADC is not used. If the ADC is used, it should be connected ATmega128A “System and Reset CC 7 ...

Page 8

... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 8151H–AVR–02/11 1. ATmega128A 8 ...

Page 9

... AVR core architecture in general. The main function of the Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega128A Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog Timer ...

Page 10

... The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses which can be accessed directly the Data Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128A has Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...

Page 11

... General Purpose Register File The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register file: 8151H–AVR–02/ R/W R/W R/W R ⊕ V ATmega128A R/W R/W R/W R SREG 11 ...

Page 12

... General R14 Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega128A 0 Addr. $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register Low Byte $1B X-register High Byte $1C Y-register Low Byte ...

Page 13

... Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ® ® AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num- ATmega128A R26 ($1A R28 ($1C) ZL ...

Page 14

... AVR ATmega128A does not support more than 64K of SRAM memory, Program memory address $0000 - $7FFF (lower 64Kbytes) is accessed by ELPM/SPM Program memory address $8000 - $FFFF (higher 64Kbytes) is accessed by ELPM/SPM , directly generated from the selected clock source for the CPU shows the parallel instruction fetches and instruction executions enabled by the Har- ...

Page 15

... Register Operands Fetch ALU Operation Execute Result Write Back ® ® AVR provides several different interrupt sources. These interrupts and the separate for details. “Boot Loader Support – Read-While-Write Self-Programming” on page ATmega128A “Memory Pro- “Interrupts” on page 59. The list also “ ...

Page 16

... AVR exits from an interrupt, it will always return to the main program and exe- ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega128A 16 ...

Page 17

... A return from an interrupt handling routine takes four clock cycles. During these 4-clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incre- mented by two, and the I-bit in SREG is set. 8151H–AVR–02/11 ; set global interrupt enable ATmega128A ® ® AVR interrupts is four clock cycles ...

Page 18

... For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega128A Program Counter (PC bits wide, thus addressing the 64K program memory locations. The ...

Page 19

... Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used. The Extended I/O space does not exist when the ATmega128A is in the ATmega103 compatibility mode. ...

Page 20

... This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 8151H–AVR–02/11 ® ® AVR ATmega128A are all accessible through all these addressing modes. “General Purpose Register File” on page Data Memory Map Memory Configuration A Data Memory $0000 - $001F ...

Page 21

... Data RD Memory access instruction ® ® AVR ATmega128A contains 4Kbytes of data EEPROM memory organized as a contains a detailed description on EEPROM programming is likely to rise or fall slowly on Power-up/down. This causes the device for some CC the EEPROM data can be corrupted because the supply voltage is CC, ...

Page 22

... The I/O space definition of the Atmel page 367. All ATmega128A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

Page 23

... The number of bits that are assigned to address high byte are fixed. • The External Memory section can not be divided into sectors with different wait-state settings. • Bus-keeper is not available. • RD, WR and ALE pins are output only (Port G in ATmega128A). 7.5.4 Using the External Memory Interface The interface consists of: • ...

Page 24

... SRAM to the AVR using ns. Refer LAXX_LD ) must not exceed address valid to ALE low (t SU External SRAM Connected to the Atmel AD7:0 ALE AVR A15 ATmega128A “I/O Ports” on page ). /t in “External Data Memory Timing” LLAXX_ST ® ® AVR D[7:0] A[7: SRAM A[15: ...

Page 25

... The most important parameters are the access time for the exter- nal memory compared to the set-up requirement of the ATmega128A. The access time for the External Memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus ...

Page 26

... Address DA7:0 (XMBK = 1) Prev. data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external). ATmega128A Address XX Data Data Data ...

Page 27

... SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external). ® ® AVR ATmega103 compatibility mode, the internal address ATmega128A Address Data Data ...

Page 28

... Memory Configuration A AVR Memory Map External 32K SRAM 0x0000 Internal Memory 0x10FF 0x1100 External 0x7FFF 0x8000 Memory 0x90FF 0x9100 (Unused) 0xFFFF ATmega128A Memory Configuration B AVR Memory Map 0x0000 0x0000 Internal Memory 0x0FFF 0x1000 0x10FF 0x1100 External 0x7FFF 0x7FFF 0x8000 Memory 0x8FFF ...

Page 29

... PC7:5 for external memory ldi r16, (0<<XMM1)|(0<<XMM0) sts XMCRB, r16 ; store 0x55 to address (OFFSET + external memory ldi r16, 0x55 sts 0x0001+OFFSET, r16 (1) 1. See “About Code Examples” on page 8. ATmega128A 29 ...

Page 30

... Read/Write Initial Value • Bits 7:4 – Reserved These bits are reserved bits in the ATmega128A and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt ...

Page 31

... When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. 8151H–AVR–02/11 ATmega128A “Boot Loader for details about boot 31 ...

Page 32

... Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega128A Table 7-2 lists the typical pro- (1) Cycles Typ Programming Time 8448 8.5ms 32 ...

Page 33

... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR SRE SRW10 SE R/W R/W R ATmega128A SM1 SM0 SM2 IVSEL R/W R/W R/W R IVCE MCUCR R/W ...

Page 34

... Sector limits with different settings of SRL2:0 SRL1 SRL0 Table 7-4. Table 7-4. ATmega128A SRL0 SRW01 SRW00 SRW11 R/W R/W R/W R Table 7-3 Sector Limits Lower sector = N/A Upper sector = 0x1100 - 0xFFFF Lower sector = 0x1100 - 0x1FFF Upper sector = 0x2000 - 0xFFFF Lower sector = 0x1100 - 0x3FFF ...

Page 35

... R Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM1 XMM0 # Bits for External Memory Address (Full 60 Kbytes space ATmega128A – – XMM2 XMM1 R R R/W R Table 28 possible to use the Released Port Pins None PC7 PC7 - PC6 PC7 - PC5 ...

Page 36

... Table 7-5. XMM2 8151H–AVR–02/11 Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM1 XMM0 # Bits for External Memory Address Address high bits ATmega128A Released Port Pins PC7 - PC4 PC7 - PC3 PC7 - PC2 Full Port C 36 ...

Page 37

... I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC Oscillator Oscillator External clock is halted, enabling TWI address reception in all sleep modes. I/O ATmega128A CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock Watchdog ...

Page 38

... ASY XDIVEN XDIV6 XDIV5 XDIV4 R/W R/W R clk ) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit CPU FLASH : CLK f = CLK ATmega128A XDIV3 XDIV2 XDIV1 R/W R/W R/W R Source clock --------------------------------- - 129 d – 0 XDIV0 XDIV R/W 0 ...

Page 39

... Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 338. Number of Watchdog Oscillator Cycles = 5.0V) Typical Time-Out (V CC 4.1ms 65ms ATmega128A ® ® AVR clock generator, and CKSEL3:0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 = 3 ...

Page 40

... Start-up Time from Power-down and Power- SUT1:0 save (1) 00 258 CK (1) 01 258 ATmega128A Table 8-3. For ceramic resonators, the XTAL2 XTAL1 GND Table 8-3. Recommended Range for Capacitors C1 and C2 for Use with Crystals – 22pF 12 - 22pF 12 - 22pF Additional Delay from Reset ( 5.0V) Recommended Usage 4 ...

Page 41

... Start-up Time from Additional Delay Power-down and from Reset (V Power-save ( ( 32K CK 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega128A Additional Delay from Reset ( 5.0V) Recommended Usage – Crystal Oscillator, BOD enabled 4.1ms Crystal Oscillator, fast ...

Page 42

... Additional Delay Power-down and from Reset Power-save (V 18CK 18CK 18CK (1) 6CK 1. This option should not be used when operating close to the maximum frequency of the device. ATmega128A XTAL2 XTAL1 GND Table Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 = 5.0V) ...

Page 43

... Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power- Additional Delay from down and Power-save The device is shipped with this option selected. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL ATmega128A 294. Nominal Frequency (MHz) 1.0 2.0 4.0 8.0 Reset (V = 5.0V) Recommended Usage CC – ...

Page 44

... CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value OSCCAL Register is not available in ATmega103 compatibility mode. ATmega128A Additional Delay from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4.1ms Fast rising power 65ms Slowly rising power ...

Page 45

... Oscillator is intended for calibration to 1.0MHz, 2.0MHz, 4.0MHz, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 8-11. OSCCAL Value 8151H–AVR–02/11 Table Internal RC Oscillator Frequency Range. Min Frequency in Percentage of Nominal Frequency (%) $00 50 $7F 75 $FF 100 ATmega128A 8-11. Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 45 ...

Page 46

... MCU wakes up and executes from the Reset Vector. 8151H–AVR–02/11 ® ® AVR provides various sleep modes allowing the user to tailor the power con- presents the different clock systems in the ATmega128A, and their distri- Active Clock Domains and Wake Up Sources in the Different Sleep Modes Active Clock Domains ...

Page 47

... The device can wake up from either Timer Overflow or Output Compare 8151H–AVR–02/11 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page ATmega128A , and clk , while allowing the CPU FLASH “External Interrupts” on page 90 39. 47 ...

Page 48

... If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to 8151H–AVR–02/11 ATmega128A , allowing operation only of asynchronous ASY 37. ...

Page 49

... Watchdog Timer. ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 70 /2, the input buffer will use excessive power. CC ATmega128A for details on how to “Internal Volt- ) are stopped, the input buffers of the ADC for ...

Page 50

... Sleep Mode Select SM1 SM0 Standby mode and Extended Standby mode are only available with external crystals or resonators. ATmega128A SM1 SM0 SM2 IVSEL R/W R/W R/W R Table 9-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby (1) Extended Standby ...

Page 51

... Reset Sources The ATmega128A has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

Page 52

... Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT TIME-OUT INTERNAL RESET ATmega128A DATA BUS MCU Control and Status Register (MCUCSR) Delay Counters CK TIMEOUT 324. The POR is activated whenever . CC 52 ...

Page 53

... POT V CC RESET TIME-OUT INTERNAL RESET “System and Reset Characteristics” on page CC ® ATmega128A has an On-chip Brown-out Detection (BOD) circuit for monitoring the = /2. BOT HYST decreases to a value below the trigger level ( Figure 10-5), the delay counter starts the MCU after the time-out period t given in “ ...

Page 54

... Analog Comparator or 8151H–AVR–02/ BOT- RESET TIME-OUT INTERNAL RESET for details on operation of the Watchdog Timer ® AVR ATmega128A features an internal bandgap reference. This reference is used for “System and Reset Characteristics” on page ATmega128A V BOT+ t TOUT . Refer to TOUT 324. To save power, the 54 ...

Page 55

... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega128A resets and executes from the Reset Vector. See To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3 different safety levels are selected by the Fuses M103C and WDTON as shown in Table 10-1 ...

Page 56

... This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. 8151H–AVR–02/11 page JTD – – JTRF R R ATmega128A (WDE bit description) must be followed WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description MCUCSR 56 ...

Page 57

... Initial Value • Bits 7:5 – Reserved These bits are reserved in the ATmega128A and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

Page 58

... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega128A Typical Time-out Typical Time-out 3. 5. 14.8ms 14.0ms 29 ...

Page 59

... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega128A. For a general explanation of the AVR interrupt handling, refer to page 15. 11.1 Interrupt Vectors in ATmega128A Table 11-1. Vector No 8151H–AVR–02/11 Reset and Interrupt Vectors Program (2) Address Source Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, ...

Page 60

... Reset Vector is in the Application section while the interrupt vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128A is: Address LabelsCode $0000 $0002 $0004 $0006 ...

Page 61

... Set stack pointer to top of RAM ldi r16, low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx :. :. :. Comments RESET:ldi r16,high(RAMEND); Main program start out SPH,r16 ; Set stack pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx jmp EXT_INT0 ; IRQ0 Handler ATmega128A 61 ...

Page 62

... Reset handler jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler :. :. ; jmp SPM_RDY ; Store Program Memory Ready Handler RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ; Set stack pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx ATmega128A Comments 62 ...

Page 63

... Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 277 ATmega128A ...

Page 64

... Enable change of interrupt vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to boot flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of interrupt vectors */ MCUCR = (1<<IVCE); /* Move interrupts to boot flash section */ MCUCR = (1<<IVSEL); ATmega128A 64 ...

Page 65

... How each alternate function interferes with the port pin is described in 8151H–AVR–02/11 and Ground as indicated in CC for a complete list of parameters. Pxn C PIN “Register Description” on page ATmega128A Figure 12-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 86 ...

Page 66

... I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 86, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega128A Figure 12 DDxn Q CLR ...

Page 67

... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega128A Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-4 ...

Page 68

... Figure 12-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is one system clock period. pd ATmega128A in r17, PINx XXX 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed ...

Page 69

... SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 ATmega128A 0xFF nop in r17, PINx 0xFF 0x00 ...

Page 70

... Figure 12-2, the digital input signal can be clamped to ground at the input of the /2. CC ATmega128A “Alternate Port Functions” on page 71. 70 ...

Page 71

... Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL ATmega128A Figure 12-6 Figure 12-2 can be overridden by PUD Q D DDxn Q ...

Page 72

... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog This is the Analog Input/output to/from alternate functions. The Input/output signal is connected directly to the pad, and can be used bi- directionally. ATmega128A , SLEEP, I/O Fig- 72 ...

Page 73

... OUTPUT • INPUT D6 INPUT – – 1. ADA is short for ADdress Active and represents the time when address is output. See nal Memory Interface” on page 22 ATmega128A PA5/AD5 PA4/AD4 SRE SRE ~(WR | ADA) • ~(WR | ADA) • PORTA5 • PUD PORTA4 • PUD SRE SRE ...

Page 74

... OC0 (Output Compare and PWM Output for Timer/Counter0) MISO (SPI Bus Master Input/Slave Output) MOSI (SPI Bus Master Output/Slave Input) SCK (SPI Bus Serial Clock) SS (SPI Slave Select input) 1. OC1C not applicable in ATmega103 compatibility mode. ATmega128A PA1/AD1 PA0/AD0 SRE SRE ~(WR | ADA) • ...

Page 75

... MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 8151H–AVR–02/11 and Table 12-7 relate the alternate functions of Port B to the overriding signals Figure 12-6 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the ATmega128A 75 ...

Page 76

... Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only. The ATmega128A is by default shipped in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled ...

Page 77

... SRE • (XMM<1) SRE • (XMM<2) A15 A14 – – – – 1. XMM = 0 in ATmega103 compatibility mode. ATmega128A PC5/A13 PC4/A12 SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM<4) A13 A12 ...

Page 78

... Interrupt2 Input or UART1 Receive Pin) (1) INT1/SDA (External Interrupt1 Input or TWI Serial DAta) (1) INT0/SCL (External Interrupt0 Input or TWI Serial CLock) 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode. ATmega128A (1) PC1/A9 PC0/A8 SRE • (XMM<7) SRE • (XMM< SRE • (XMM<7) SRE • ...

Page 79

... I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 12-12 shown in 8151H–AVR–02/11 and Table 12-13 relates the alternate functions of Port D to the overriding signals Figure 12-6 on page 71. ATmega128A 79 ...

Page 80

... When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega128A PD5/XCK1 PD4/ICP1 ...

Page 81

... Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3) (1) AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock input/output) PDO/TXD0 (Programming Data Output or UART0 Transmit Pin) PDI/RXD0 (Programming Data Input or UART0 Receive Pin) 1. ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 compatibility mode. ATmega128A Table 12-14. 81 ...

Page 82

... Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega128A. TXD0, UART0 Transmit pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega128A ...

Page 83

... ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel ATmega128A PE1/PDO/TXD0 PE0/PDI/RXD0 TXEN0 RXEN0 0 PORTE0 • PUD TXEN0 ...

Page 84

... JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI/ADC7 INPUT ADC6 INPUT PF3/ADC3 PF2/ADC2 – – ADC3 INPUT ADC2 INPUT ATmega128A . . PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN JTAGEN JTAGEN 0 0 – – TMS/ADC5 INPUT TCKADC4 INPUT PF1/ADC1 PF0/ADC0 ...

Page 85

... RD is the external data memory read control strobe. • WR – Port G, Bit the external data memory write control strobe. 8151H–AVR–02/11 Alternate Function TOSC1 (RTC Oscillator Timer/Counter0) TOSC2 (RTC Oscillator Timer/Counter0) ALE (Address Latch Enable to external memory) RD (Read strobe to external memory) WR (Write strobe to external memory) ATmega128A 85 ...

Page 86

... Port G to the overriding signals Figure 12-6 on page 71. PG4/TOSC1 AS0 0 AS0 AS0 0 – T/C0 OSC INPUT TSM – – R for more details about this feature. ATmega128A PG3/TOSC2 PG2/ALE AS0 SRE 0 0 AS0 SRE SRE 0 ALE AS0 – – T/C0 OSC OUTPUT – PG0/WR SRE 0 SRE ...

Page 87

... PINB7 PINB6 PINB5 PINB4 N/A N/A N/A N PORTC7 PORTC6 PORTC5 PORTC4 R/W R/W R/W R DDC7 DDC6 DDC5 DDC4 R/W R/W R/W R ATmega128A PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R PINA3 PINA2 PINA1 PINA0 N/A ...

Page 88

... PORTE5 PORTE4 R/W R/W R/W R DDE7 DDE6 DDE5 DDE4 R/W R/W R/W R PINE7 PINE6 PINE5 PINE4 N/A N/A N/A N/A ATmega128A PINC3 PINC2 PINC1 PINC0 N/A N/A N/A N PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W ...

Page 89

... R R N/A N/A N/A N – – – PORTG4 R – – – DDG4 R – – – PING4 N/A ATmega128A PORTF3 PORTF2 PORTF1 PORTF0 R/W R/W R/W R DDF3 DDF2 DDF1 DDF0 R/W R/W R/W R PINF3 PINF2 PINF1 PINF0 N/A N/A N/A N PORTG3 PORTG2 ...

Page 90

... If the level is sampled twice by the Watchdog Oscillator clock but ISC31 ISC30 ISC21 ISC20 R/W R/W R/W R Table 13-1. Edges on INT3:INT0 are registered asynchro- ATmega128A 37. Low level interrupts and the 321. The MCU will “Clock Systems and ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R ...

Page 91

... The falling edge between two samples of INTn generates an interrupt request. 1 The rising edge between two samples of INTn generates an interrupt request When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. ATmega128A Condition Min Typ 50 4 ...

Page 92

... Enable and Sleep Modes” on page 70 8151H–AVR–02/ INT7 INT6 INT5 INT4 R/W R/W R/W R INTF7 INTF6 INTF5 INTF4 R/W R/W R/W R for more information. ATmega128A INT3 INT2 INT1 IINT0 R/W R/W R/W R INTF3 INTF2 INTF1 IINTF0 R/W R/W R/W R “Digital Input EIMSK ...

Page 93

... Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn Synchronized Status flags Status flags ASSRn asynchronous mode select (ASn) ATmega128A Figure 14-1. For the actual placement of TOVn (Int.Req.) clk Tn TOSC1 T/C Oscillator Prescaler TOSC2 clk OCn I/O (Int.Req.) Waveform OCn ...

Page 94

... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T0 109. For details on clock sources and prescaler, see 106. ATmega128A See “Output Compare . When the AS0 I/O “ASSR Figure 94 ...

Page 95

... present or not. A CPU write overrides (has priority over) all counter clear or T0 98. 98). Figure 14-3 shows a block diagram of the output compare unit. ATmega128A TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top (“Modes of Operation” ...

Page 96

... Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the compare match will be missed, resulting in incorrect waveform gen- 8151H–AVR–02/11 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega128A TCNTn OCFn (Int.Req.) OCxy 96 ...

Page 97

... The design of the output compare pin logic allows initialization of the OC0 state before the out- put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. 8151H–AVR–02/11 COMn1 Waveform COMn0 Generator FOCn clk I/O See “Register Description” on page 106. ATmega128A Figure 14-4 shows a simplified schematic OCn PORT D ...

Page 98

... Table 14-5 on page 97.). “Timer/Counter Timing Diagrams” on page TOV0 flag, the timer resolution can be increased by software. There TOV0 Figure ATmega128A Table 14-4 on page 108. 102. ) will be set in the same TOV0 flag in this case behaves like a ninth 14-5. The counter value (TCNT0) ...

Page 99

... PWM mode is shown in 8151H–AVR–02/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + flag is set in the same timer clock cycle that the TOV0 Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- ATmega128A OCn Interrupt Flag Set (COMn1 OC0 clk_I ...

Page 100

... PWM mode. 8151H–AVR–02/ set each time the counter reaches Max If the interrupt TOV0 Table 14-4 on page f = OCnPWM = f oc0 ATmega128A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 108). The actual OC0 value f clk_I/O ----------------- - ⋅ ...

Page 101

... OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The 8151H–AVR–02/ set each time the counter reaches BOTTOM. The TOV0 Table 14-5 on page ATmega128A Figure 14-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 108) ...

Page 102

... Timer/Counter operation. The show the same timing data, but with the prescaler enabled. The figures illustrate contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 ATmega128A f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 14-7 ...

Page 103

... I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ATmega128A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 103 ...

Page 104

... OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. 8151H–AVR–02/11 caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega128A TOP BOTTOM BOTTOM + 1 TOP 104 ...

Page 105

... The output compare pin is changed on the timer clock and is not synchronized to the processor clock. 8151H–AVR–02/11 ) again becomes active, TCNT0 will read as the previous value (before entering I/O ATmega128A 105 ...

Page 106

... By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked I/O /256, and clk /1024. Additionally, clk T0S T0S FOC0 WGM00 COM01 W R/W R ATmega128A 10-BIT T/C PRESCALER 0 TIMER/COUNTER0 CLOCK SOURCE clk T0 . clk is by default connected to the main T0 T0 /8, clk T0S as well as 0 (stop) may be selected. T0S ...

Page 107

... COM00 Description 0 0 Normal port operation, OC0 disconnected Toggle OC0 on compare match 1 0 Clear OC0 on compare match 1 1 Set OC0 on compare match ATmega128A Table 14-2 and “Modes of Operation” Update of TOV0 Flag TOP OCR0 at Set on 0xFF Immediate MAX 0xFF TOP BOTTOM ...

Page 108

... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See 101 for more details. ATmega128A (1) “Fast PWM Mode” on page 99 (1) “Phase Correct PWM Mode” on page ...

Page 109

... T0S 1 0 clk /256 (From prescaler clk /1024 (From prescaler TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R – – – – ATmega128A R/W R/W R/W R R/W R/W R/W R AS0 TCN0UB OCR0UB TCR0UB R When AS0 is I/O TCNT0 OCR0 ASSR 109 ...

Page 110

... Alternatively, OCF0 is cleared by writing a logic one to 8151H–AVR–02/ OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega128A OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R TIMSK ...

Page 111

... If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. 8151H–AVR–02/ TSM – – – R ATmega128A ACME PUD PSR0 PSR321 SFIOR R/W R/W R/W R 111 ...

Page 112

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the 8151H–AVR–02/11 “Pin Configurations” on page “Register Description” on page 134. ATmega128A Figure 15-1. For the actual 2. CPU accessible I/O Registers, 112 ...

Page 113

... Clear Control Logic Direction Timer/Counter TCNTx = OCRxA = OCRxB = OCRxC ICRx TCCRxA Refer to Figure 1-1 on page 2, Table 12-5 on page Timer/Counter1 and 3 pin placement and description. ATmega128A TOVx (Int.Req.) Clock Select TCLK Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCFxA (Int.Req.) Waveform Generation OCFxB Fixed (Int ...

Page 114

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. ATmega128A (See 114 ...

Page 115

... The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. 8151H–AVR–02/11 ATmega128A 115 ...

Page 116

... TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH :. (1) unsigned int Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn See “About Code Examples” on page 8. The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega128A 116 ...

Page 117

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 8. ATmega128A 117 ...

Page 118

... Set TCNTn TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page 8. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn. shows a block diagram of the counter and its surroundings. ATmega128A 145. 118 ...

Page 119

... Signalize that TCNTn has reached maximum value. Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock present or not. A CPU write overrides (has priority over) all counter clear ATmega128A TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM “ ...

Page 120

... ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3. ATmega128A Figure 15-3. The elements of DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES ...

Page 121

... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn 8151H–AVR–02/11 115. ATmega128A “Accessing 16-bit Registers” (Figure 16-1 on page 145). The edge detector is also ...

Page 122

... The small “n” in the register and DATABUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega128A (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 COMnx1:0 ...

Page 123

... The OCnx Register keeps its value even when changing between waveform generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 8151H–AVR–02/11 115. ATmega128A “Accessing 16-bit Registers” 123 ...

Page 124

... COMnx1 Waveform COMnx0 D Generator FOCnx OCnx D PORT D DDR clk I/O See “Register Description” on page 134. Table 15-2 on page ATmega128A Figure 15-5 shows a simplified Q 1 OCnx Pin Table 15-2, Table 15-3 and Table 15-4 135. For fast PWM mode refer to ...

Page 125

... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. 8151H–AVR–02/11 ATmega128A 124.) “Timer/Counter Timing Diagrams” on page Figure 15-6. The counter value (TCNTn) 132 ...

Page 126

... PWM mode well suited for power regulation, rectification, and DAC 8151H–AVR–02/11 TCNTn OCnA (Toggle) Period when OCRnA is set to zero (0x0000). The waveform frequency clk_I OCnA ATmega128A OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O -------------------------------------------------- - ⋅ ⋅ OCRnA 1 ...

Page 127

... TOP log R = ---------------------------------- - FPWM log ATmega128A ) + Figure 15-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

Page 128

... PWM modes, these modes are preferred for motor control applications. 8151H–AVR–02/11 Table 15-3 on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCRnA is set to zero (0x0000). This feature clk_I/O n ATmega128A 135). The actual OCnx ) 128 ...

Page 129

... TOP log ---------------------------------- - PCPWM log Figure 15-8 illustrates, changing the TOP actively ATmega128A Figure 15-8. The figure OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 129 ...

Page 130

... ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: 8151H–AVR–02/11 f OCnxPCPWM 15-9). ATmega128A Table 15-4 on page f clk_I/O = --------------------------- - ⋅ ...

Page 131

... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega128A ( ) TOP + log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update ...

Page 132

... OCRnx OCFnx Figure 15-11 8151H–AVR–02/11 f OCnxPFCPWM Figure 15-10 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ATmega128A f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value ...

Page 133

... Tn (clk /1) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value shows the same timing data, but with the prescaler enabled. ATmega128A OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 133 ...

Page 134

... TOP) OCRnx Old OCRnx Value COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R COM3A1 COM3A0 COM3B1 COM3B0 R/W R/W R Table 15-2 ATmega128A /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1C1 COM1C0 WGM11 R/W R/W R/W R COM3C1 COM3C0 WGM31 R/W R/W ...

Page 135

... COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 126. shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase ATmega128A Description Normal port operation, OCnA/OCnB/OCnC disconnected. ...

Page 136

... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct ATmega128A Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3 11: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected. Clear OCnA/OCnB/OCnC on compare match when up-counting ...

Page 137

... Fast PWM 1 1 Fast PWM ICNC1 ICES1 – R/W R ICNC3 ICES3 – R/W R ATmega128A Update of (1) x TOP OCRn ICRn Immediate – – ICRn BOTTOM OCRnA BOTTOM WGM n2:0 definitions. However, the functionality and WGM13 WGM12 CS12 CS11 R/W R/W R/W R/W ...

Page 138

... I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge 1 1 External clock source on Tn pin. Clock on rising edge FOC1A FOC1B FOC1C FOC3A FOC3B FOC3C ATmega128A – – – – – – – – Figure 0 – TCCR1C ...

Page 139

... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R TCNT3[15:8] TCNT3[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R ATmega128A R/W R/W R/W R R/W R/W R/W R See “Accessing 16 R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L TCNT3H TCNT3L OCR1AH ...

Page 140

... OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R OCR3B[15:8] OCR3B[7:0] R/W R/W R/W R OCR3C[15:8] OCR3C[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 115 ICR1[15:8] ICR1[7:0] R/W R/W R/W R ATmega128A R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W ...

Page 141

... R/W R This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. 59.) is executed when the ICF1 flag, located in TIFR, is set. ATmega128A ICR3[15:8] ICR3[7:0] R/W R/W ...

Page 142

... Timer/Counter1 Output Compare C Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 59) is executed when the OCF1C flag, located in ETIFR, is set. 8151H–AVR–02/ – – TICIE3 This register is not available in ATmega103 compatibility mode. ATmega128A OCIE3A OCIE3B TOIE3 OCIE3C R/W R/W R/W R ...

Page 143

... This register contains flag bits for several Timer/Counters, but only timer 1 bits are described in this section. The remaining bits are described in their respective timer sections – – ICF3 R/W R/W R ATmega128A OCF1A OCF1B TOV1 OCF0 R/W R/W R/W R Table 15-5 on page 136 ...

Page 144

... Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is exe- cuted. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. 8151H–AVR–02/11 ATmega128A Table 14-2 on page 107 for the TOV3 flag 144 ...

Page 145

... Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O /clk ). The Tn pin is sampled once every system clock cycle by the pin synchroniza /clk I/O Synchronization ATmega128A CLK_I/O /clk pulse for each positive (CSn2 nega Edge Detector /8, f /64, CLK_I/O Figure ) ...

Page 146

... CK PSR321 T2 0 CS20 CS31 CS21 CS22 TIMER/COUNTER3 CLOCK SOURCE clk T3 The synchronization logic on the input pins ( TSM – – R ATmega128A 10-BIT T/C PRESCALER Clear CS10 CS11 CS12 TIMER/COUNTER2 CLOCK SOURCE TIMER/COUNTER1 CLOCK SOURCE clk T2 T3/T2/T1) is shown in Figure 16- – ACME PUD PSR0 ...

Page 147

... Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a reset of this prescaler will affect all three timers. 8151H–AVR–02/11 ATmega128A 147 ...

Page 148

... CPU accessible I/O registers, including I/O bits 159. TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn ATmega128A Figure 17-1. For the actual placement of TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCn (Int.Req.) Waveform OCn Generation ...

Page 149

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. ATmega128A ). T2 See “Output Compare 145 ...

Page 150

... Signalize that TCNT2 has reached maximum value. Signalize that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 153. ATmega128A TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) top in the following ...

Page 151

... TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 8151H–AVR–02/11 Figure 17-3 DATA BUS OCRn TCNTn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega128A shows a block diagram of the OCFn (Int.Req.) OCn 151 ...

Page 152

... Note that some COM21:0 bit settings are reserved for certain modes of operation. 8151H–AVR–02/11 COMn1 Waveform COMn0 D Generator FOCn D PORT D clk I/O See “Register Description” on page 159. ATmega128A Figure 17-4 shows a simplified schematic Q 1 OCn DDR OCn Pin 152 ...

Page 153

... For fast PWM mode, refer to Table 17-5 on page Figure 17-8, Figure 157. TOV 2 flag, the timer resolution can be increased by software. There TOV Figure ATmega128A Table 17-4 on page 161. 17-9, Figure 17-10, and Figure 17-11 2) will be set in the same TOV 2 flag in this case behaves like a ninth 17-5 ...

Page 154

... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in 8151H–AVR–02/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + Figure 17-6. The TCNT2 value is in the timing diagram shown as a his- ATmega128A OCn Interrupt Flag Set (COMn1 OC2 clk_I 154 ...

Page 155

... PWM mode. 8151H–AVR–02/ Table 17-4 on page ----------------- - OCnPWM N 256 = f OC2 ATmega128A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 160). The actual OC2 value clk_I/O ⋅ /2 when OCR2 is set to zero. This fea- clk_I/O ...

Page 156

... OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the compare 8151H–AVR–02/ Table 17-5 on page ATmega128A Figure 17-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 161) ...

Page 157

... Figure 17-7 Figure 17-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega128A f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 17-7. When the OCR2A value is MAX the ...

Page 158

... I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ATmega128A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 158 ...

Page 159

... Pulse Width Modulation (PWM) modes. See on page 8151H–AVR–02/11 caler (f /8) clk_I/O I/O Tn /8) I/O TOP - FOC2 WGM20 COM21 W R/W R 153. ATmega128A TOP BOTTOM TOP COM20 WGM21 CS22 CS21 R/W R/W R/W R Table 17-2 and “Modes of Operation” BOTTOM + 1 ...

Page 160

... Set OC2 on compare match, clear OC2 at BOTTOM, (inverting mode special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. See for more details. ATmega128A Update of TOV2 Flag TOP OCR2 at ...

Page 161

... I clk /1024 (From prescaler) I External clock source on T2 pin. Clock on falling edge 1 1 External clock source on T2 pin. Clock on rising edge R/W R/W R ATmega128A (1) “Phase Correct PWM Mode” on page TCNT2[7:0] R/W R/W R/W R TCNT2 R/W 0 161 ...

Page 162

... OCR2[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega128A R/W R/W R/W R OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R OCR2 TIMSK ...

Page 163

... Timer/Counter units and the port B pin 7 output driver circuit. 8151H–AVR–02/11 “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” and “8-bit Timer/Counter2 with PWM” on page Timer/Counter 1 OC1C Timer/Counter 2 OC2 (Figure 18-1). ATmega128A 148. Note that this feature is not Pin OC1C / OC2 / PB7 Figure 18-2. The schematic 163 ...

Page 164

... D Q OC1C D Q OC2 D Q PORTB7 DATABUS illustrates the modulator in action. In this example the Timer/Counter1 is set to oper- clk I/O OC1C OC2 PB7 PB7 1 (Period) ATmega128A Vcc Modulator OC2 / PB7 D Q DDRB7 2 3 Pin OC1C / Figure 164 ...

Page 165

... Double Speed (CK/2) Master SPI Mode 19.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega128A and peripheral devices or between several AVR devices. Figure 19-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two Shift Registers, and a Master clock generator ...

Page 166

... High period: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page 8151H–AVR–02/11 Table 19-1. For more details on automatic port overrides, refer to 71. ATmega128A SHIFT ENABLE “Alternate Port 166 ...

Page 167

... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 74 direction of the user defined SPI pins. ATmega128A Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 167 ...

Page 168

... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page ATmega128A 8. 168 ...

Page 169

... Read received data and return r16,SPDR in ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page ATmega128A 8. 169 ...

Page 170

... Data bits are shifted out and latched in on opposite edges of the SCK signal, Table 19-3, as done below: Leading edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) ATmega128A Figure Table Trailing edge SPI mode Setup (Falling) 0 Sample (Falling) 1 ...

Page 171

... CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit SPIE SPE DORD R/W R/W R ATmega128A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 2 Bit 3 Bit 4 Bit MSTR ...

Page 172

... CPHA functionality CPHA Leading edge 0 Sample 1 Setup Relationship Between SCK and the Oscillator Frequency SPR1 ATmega128A for an example. The CPOL functionality is summarized Trailing edge Falling Rising and Figure 2 for an example. The CPHA functional- Trailing edge Setup Sample SPR0 SCK Frequency osc f ...

Page 173

... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega128A is also used for program memory and EEPROM down- loading or uploading. See 19.5.3 SPDR - SPI Data Register ...

Page 174

... Dual USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The ATmega128A has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O registers as shown in compatibility mode, USART1 is not available, neither is the UBRR0H or UCRS0C Registers ...

Page 175

... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Refer to Figure 1-1 on page 2, Table 12-11 on page pin placement. ATmega128A Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN ...

Page 176

... Figure 20-2. Clock Generation Logic, Block Diagram 8151H–AVR–02/11 shows a block diagram of the clock generation logic. UBRR fosc UBRR+1 Prescaling Down-Counter OSC Sync Edge Register Detector xcki XCK xcko Pin DDR_XCK UCPOL ATmega128A Figure 20-1) if the buffer registers are U2X / DDR_XCK 0 UMSEL txclk rxclk ...

Page 177

... BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps). Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRH and UBRRL Registers 4095) 198). ATmega128A Figure 20-2. Equation for Calculating (1) Baud Rate UBRR Value ...

Page 178

... XCK edge and sampled at rising XCK edge. 8151H–AVR–02/11 Figure 20-2 for details. f XCK depends on the stability of the system clock source therefore recommended to osc XCK RxD / TxD XCK RxD / TxD Figure 20-3 shows, when UCPOL is zero the data will be changed at ATmega128A f OSC < ---------- - 4 Sample Sample 178 ...

Page 179

... No transfers on the communication line (RxD or TxD). An IDLE line must be high. ⊕ … even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity ATmega128A FRAME [5] [6] [7] [8] [P] Sp1 [Sp2] ⊕ ⊕ ⊕ ⊕ ⊕ ...

Page 180

... The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 8151H–AVR–02/11 Data bit n of the character ATmega128A 180 ...

Page 181

... More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATmega128A 8. 181 ...

Page 182

... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page ATmega128A 8. 182 ...

Page 183

... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega128A 183 ...

Page 184

... The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used. 8151H–AVR–02/11 ATmega128A 184 ...

Page 185

... Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page The function simply waits for data to be present in the receive buffer by checking the RXC flag, before reading the buffer and returning the value. ATmega128A 8. 185 ...

Page 186

... Code Examples” on page The receive function example reads all the I/O registers into the register file before any compu- tation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega128A 8. 186 ...

Page 187

... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to check if the frame had a Parity Error. 8151H–AVR–02/11 and “Parity Checker” on page 187. ATmega128A 187 ...

Page 188

... The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. ATmega128A 8. Figure 20-5 ...

Page 189

... Note that the receiver only uses the first stop bit of a frame. the stop bit and the earliest possible beginning of the start bit of the next frame. 8151H–AVR–02/11 IDLE Figure 20-6 shows the sampling of the data bits and the par ATmega128A START BIT Figure 20-7 shows the sampling of ...

Page 190

... Table 20-3 list the maximum receiver baud rate error that can be tolerated. Note ATmega128A STOP 1 (A) (B) ( ...

Page 191

... ATmega128A Max Total Recommended Max Error % Receiver Error % +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Max Total Recommended Max ...

Page 192

... The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer 8151H–AVR–02/ RXBn[7:0] TXBn[7:0] R/W R/W R/W R ATmega128A R/W R/W R/W R UDRn (Read) UDRn (Write) 192 ...

Page 193

... This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. 8151H–AVR–02/ RXCn TXCn UDREn FEn R R ATmega128A DORn UPEn U2Xn MPCMn R R R/W R UCSRnA 193 ...

Page 194

... RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn and UPEn flags. 8151H–AVR–02/11 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega128A 191 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 194 ...

Page 195

... Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting mismatch is detected, the UPEn flag in UCSRnA will be set. 8151H–AVR–02/ – UMSELn UPMn1 UPMn0 R/W R/W R UMSELn Bit Settings UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega128A USBSn UCSZn1 UCSZn0 R/W R/W R/W R UCPOLn UCSRnC R/W 0 195 ...

Page 196

... UCSZn Bits Settings UCSZn1 UCPOLn Bit Settings Transmitted Data Changed (Output of TxDn Pin) Rising XCKn Edge Falling XCKn Edge ATmega128A Parity Mode Disabled (Reserved) Enabled, Even Parity Enabled, Odd Parity Stop Bit(s) 1-bit 2-bits UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved ...

Page 197

... Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler. 8151H–AVR–02/ – – – – UBRRn[7: R/W R/W R/W R ATmega128A UBRRn[11: R/W R/W R/W R/W R/W R/W R/W R UBRRnH UBRRnL 197 ...

Page 198

... ATmega128A Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 ...

Page 199

... ATmega128A f = 7.3728MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0.0% 25 0. ...

Page 200

... ATmega128A MHz f = 14.7456MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 2 -7.8% 1 -7.8% – – 0 -7.8% 1.3824Mbps 921.6Kbps = 16.0000MHz U2X = 1 UBRR 832 416 207 138 ...

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